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-rw-r--r--include/os/linux/ioctl_ctrl.c2106
1 files changed, 2106 insertions, 0 deletions
diff --git a/include/os/linux/ioctl_ctrl.c b/include/os/linux/ioctl_ctrl.c
new file mode 100644
index 0000000..ee141ff
--- /dev/null
+++ b/include/os/linux/ioctl_ctrl.c
@@ -0,0 +1,2106 @@
1/*
2 * Copyright (c) 2011-2020, NVIDIA Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/uaccess.h>
18#include <linux/cdev.h>
19#include <linux/file.h>
20#include <linux/anon_inodes.h>
21#include <linux/fs.h>
22#include <linux/pm_runtime.h>
23#include <uapi/linux/nvgpu.h>
24
25#include <nvgpu/bitops.h>
26#include <nvgpu/kmem.h>
27#include <nvgpu/bug.h>
28#include <nvgpu/ptimer.h>
29#include <nvgpu/vidmem.h>
30#include <nvgpu/log.h>
31#include <nvgpu/enabled.h>
32#include <nvgpu/sizes.h>
33#include <nvgpu/list.h>
34#include <nvgpu/clk_arb.h>
35#include <nvgpu/gk20a.h>
36#include <nvgpu/channel.h>
37
38#include "ioctl_ctrl.h"
39#include "ioctl_dbg.h"
40#include "ioctl_as.h"
41#include "ioctl_tsg.h"
42#include "ioctl_channel.h"
43#include "gk20a/fence_gk20a.h"
44
45#include "platform_gk20a.h"
46#include "os_linux.h"
47#include "dmabuf.h"
48#include "channel.h"
49#include "dmabuf_vidmem.h"
50
51#define HZ_TO_MHZ(a) ((a > 0xF414F9CD7ULL) ? 0xffff : (a >> 32) ? \
52 (u32) ((a * 0x10C8ULL) >> 32) : (u16) ((u32) a/MHZ))
53#define MHZ_TO_HZ(a) ((u64)a * MHZ)
54
55struct gk20a_ctrl_priv {
56 struct device *dev;
57 struct gk20a *g;
58 struct nvgpu_clk_session *clk_session;
59
60 struct nvgpu_list_node list;
61 struct {
62 struct vm_area_struct *vma;
63 unsigned long flags;
64 bool vma_mapped;
65 } usermode_vma;
66};
67
68static inline struct gk20a_ctrl_priv *
69gk20a_ctrl_priv_from_list(struct nvgpu_list_node *node)
70{
71 return (struct gk20a_ctrl_priv *)
72 ((uintptr_t)node - offsetof(struct gk20a_ctrl_priv, list));
73}
74
75static u32 gk20a_as_translate_as_alloc_flags(struct gk20a *g, u32 flags)
76{
77 u32 core_flags = 0;
78
79 if (flags & NVGPU_GPU_IOCTL_ALLOC_AS_FLAGS_USERSPACE_MANAGED)
80 core_flags |= NVGPU_AS_ALLOC_USERSPACE_MANAGED;
81
82 return core_flags;
83}
84
85int gk20a_ctrl_dev_open(struct inode *inode, struct file *filp)
86{
87 struct nvgpu_os_linux *l;
88 struct gk20a *g;
89 struct gk20a_ctrl_priv *priv;
90 int err = 0;
91
92 l = container_of(inode->i_cdev,
93 struct nvgpu_os_linux, ctrl.cdev);
94 g = gk20a_get(&l->g);
95 if (!g)
96 return -ENODEV;
97
98 nvgpu_log_fn(g, " ");
99
100 priv = nvgpu_kzalloc(g, sizeof(struct gk20a_ctrl_priv));
101 if (!priv) {
102 err = -ENOMEM;
103 goto free_ref;
104 }
105 filp->private_data = priv;
106 priv->dev = dev_from_gk20a(g);
107 /*
108 * We dont close the arbiter fd's after driver teardown to support
109 * GPU_LOST events, so we store g here, instead of dereferencing the
110 * dev structure on teardown
111 */
112 priv->g = g;
113
114 if (!g->sw_ready) {
115 err = gk20a_busy(g);
116 if (err)
117 goto free_ref;
118 gk20a_idle(g);
119 }
120
121 err = nvgpu_clk_arb_init_session(g, &priv->clk_session);
122free_ref:
123 if (err != 0) {
124 gk20a_put(g);
125 if (priv)
126 nvgpu_kfree(g, priv);
127 } else {
128 nvgpu_mutex_acquire(&l->ctrl.privs_lock);
129 nvgpu_list_add(&priv->list, &l->ctrl.privs);
130 nvgpu_mutex_release(&l->ctrl.privs_lock);
131 }
132
133 return err;
134}
135int gk20a_ctrl_dev_release(struct inode *inode, struct file *filp)
136{
137 struct gk20a_ctrl_priv *priv = filp->private_data;
138 struct gk20a *g = priv->g;
139 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
140
141 nvgpu_log_fn(g, " ");
142
143 nvgpu_mutex_acquire(&l->ctrl.privs_lock);
144 nvgpu_list_del(&priv->list);
145 nvgpu_mutex_release(&l->ctrl.privs_lock);
146
147 if (priv->clk_session)
148 nvgpu_clk_arb_release_session(g, priv->clk_session);
149
150 gk20a_put(g);
151 nvgpu_kfree(g, priv);
152
153 return 0;
154}
155
156struct nvgpu_flags_mapping {
157 u64 ioctl_flag;
158 int enabled_flag;
159};
160
161static struct nvgpu_flags_mapping flags_mapping[] = {
162 {NVGPU_GPU_FLAGS_CAN_RAILGATE,
163 NVGPU_CAN_RAILGATE},
164 {NVGPU_GPU_FLAGS_HAS_SYNCPOINTS,
165 NVGPU_HAS_SYNCPOINTS},
166 {NVGPU_GPU_FLAGS_SUPPORT_PARTIAL_MAPPINGS,
167 NVGPU_SUPPORT_PARTIAL_MAPPINGS},
168 {NVGPU_GPU_FLAGS_SUPPORT_SPARSE_ALLOCS,
169 NVGPU_SUPPORT_SPARSE_ALLOCS},
170 {NVGPU_GPU_FLAGS_SUPPORT_SYNC_FENCE_FDS,
171 NVGPU_SUPPORT_SYNC_FENCE_FDS},
172 {NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS,
173 NVGPU_SUPPORT_CYCLE_STATS},
174 {NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS_SNAPSHOT,
175 NVGPU_SUPPORT_CYCLE_STATS_SNAPSHOT},
176 {NVGPU_GPU_FLAGS_SUPPORT_USERSPACE_MANAGED_AS,
177 NVGPU_SUPPORT_USERSPACE_MANAGED_AS},
178 {NVGPU_GPU_FLAGS_SUPPORT_TSG,
179 NVGPU_SUPPORT_TSG},
180 {NVGPU_GPU_FLAGS_SUPPORT_CLOCK_CONTROLS,
181 NVGPU_SUPPORT_CLOCK_CONTROLS},
182 {NVGPU_GPU_FLAGS_SUPPORT_GET_VOLTAGE,
183 NVGPU_SUPPORT_GET_VOLTAGE},
184 {NVGPU_GPU_FLAGS_SUPPORT_GET_CURRENT,
185 NVGPU_SUPPORT_GET_CURRENT},
186 {NVGPU_GPU_FLAGS_SUPPORT_GET_POWER,
187 NVGPU_SUPPORT_GET_POWER},
188 {NVGPU_GPU_FLAGS_SUPPORT_GET_TEMPERATURE,
189 NVGPU_SUPPORT_GET_TEMPERATURE},
190 {NVGPU_GPU_FLAGS_SUPPORT_SET_THERM_ALERT_LIMIT,
191 NVGPU_SUPPORT_SET_THERM_ALERT_LIMIT},
192 {NVGPU_GPU_FLAGS_SUPPORT_DEVICE_EVENTS,
193 NVGPU_SUPPORT_DEVICE_EVENTS},
194 {NVGPU_GPU_FLAGS_SUPPORT_FECS_CTXSW_TRACE,
195 NVGPU_SUPPORT_FECS_CTXSW_TRACE},
196 {NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_SUBMIT_NO_JOBTRACKING,
197 NVGPU_SUPPORT_DETERMINISTIC_SUBMIT_NO_JOBTRACKING},
198 {NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_SUBMIT_FULL,
199 NVGPU_SUPPORT_DETERMINISTIC_SUBMIT_FULL},
200 {NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_OPTS,
201 NVGPU_SUPPORT_DETERMINISTIC_OPTS},
202 {NVGPU_GPU_FLAGS_SUPPORT_SYNCPOINT_ADDRESS,
203 NVGPU_SUPPORT_SYNCPOINT_ADDRESS},
204 {NVGPU_GPU_FLAGS_SUPPORT_USER_SYNCPOINT,
205 NVGPU_SUPPORT_USER_SYNCPOINT},
206 {NVGPU_GPU_FLAGS_SUPPORT_USERMODE_SUBMIT,
207 NVGPU_SUPPORT_USERMODE_SUBMIT},
208 {NVGPU_GPU_FLAGS_SUPPORT_IO_COHERENCE,
209 NVGPU_SUPPORT_IO_COHERENCE},
210 {NVGPU_GPU_FLAGS_SUPPORT_RESCHEDULE_RUNLIST,
211 NVGPU_SUPPORT_RESCHEDULE_RUNLIST},
212 {NVGPU_GPU_FLAGS_SUPPORT_MAP_DIRECT_KIND_CTRL,
213 NVGPU_SUPPORT_MAP_DIRECT_KIND_CTRL},
214 {NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF,
215 NVGPU_ECC_ENABLED_SM_LRF},
216 {NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM,
217 NVGPU_ECC_ENABLED_SM_SHM},
218 {NVGPU_GPU_FLAGS_ECC_ENABLED_TEX,
219 NVGPU_ECC_ENABLED_TEX},
220 {NVGPU_GPU_FLAGS_ECC_ENABLED_LTC,