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-rw-r--r--include/os/linux/ioctl.c297
1 files changed, 0 insertions, 297 deletions
diff --git a/include/os/linux/ioctl.c b/include/os/linux/ioctl.c
deleted file mode 100644
index a40df2a..0000000
--- a/include/os/linux/ioctl.c
+++ /dev/null
@@ -1,297 +0,0 @@
1/*
2 * NVGPU IOCTLs
3 *
4 * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <linux/file.h>
20
21#include <nvgpu/nvgpu_common.h>
22#include <nvgpu/ctxsw_trace.h>
23#include <nvgpu/gk20a.h>
24
25#include "gk20a/dbg_gpu_gk20a.h"
26
27#include "ioctl_channel.h"
28#include "ioctl_ctrl.h"
29#include "ioctl_as.h"
30#include "ioctl_tsg.h"
31#include "ioctl_dbg.h"
32#include "module.h"
33#include "os_linux.h"
34#include "ctxsw_trace.h"
35#include "platform_gk20a.h"
36
37#define GK20A_NUM_CDEVS 7
38
39const struct file_operations gk20a_channel_ops = {
40 .owner = THIS_MODULE,
41 .release = gk20a_channel_release,
42 .open = gk20a_channel_open,
43#ifdef CONFIG_COMPAT
44 .compat_ioctl = gk20a_channel_ioctl,
45#endif
46 .unlocked_ioctl = gk20a_channel_ioctl,
47};
48
49static const struct file_operations gk20a_ctrl_ops = {
50 .owner = THIS_MODULE,
51 .release = gk20a_ctrl_dev_release,
52 .open = gk20a_ctrl_dev_open,
53 .unlocked_ioctl = gk20a_ctrl_dev_ioctl,
54#ifdef CONFIG_COMPAT
55 .compat_ioctl = gk20a_ctrl_dev_ioctl,
56#endif
57 .mmap = gk20a_ctrl_dev_mmap,
58};
59
60static const struct file_operations gk20a_dbg_ops = {
61 .owner = THIS_MODULE,
62 .release = gk20a_dbg_gpu_dev_release,
63 .open = gk20a_dbg_gpu_dev_open,
64 .unlocked_ioctl = gk20a_dbg_gpu_dev_ioctl,
65 .poll = gk20a_dbg_gpu_dev_poll,
66#ifdef CONFIG_COMPAT
67 .compat_ioctl = gk20a_dbg_gpu_dev_ioctl,
68#endif
69};
70
71static const struct file_operations gk20a_as_ops = {
72 .owner = THIS_MODULE,
73 .release = gk20a_as_dev_release,
74 .open = gk20a_as_dev_open,
75#ifdef CONFIG_COMPAT
76 .compat_ioctl = gk20a_as_dev_ioctl,
77#endif
78 .unlocked_ioctl = gk20a_as_dev_ioctl,
79};
80
81/*
82 * Note: We use a different 'open' to trigger handling of the profiler session.
83 * Most of the code is shared between them... Though, at some point if the
84 * code does get too tangled trying to handle each in the same path we can
85 * separate them cleanly.
86 */
87static const struct file_operations gk20a_prof_ops = {
88 .owner = THIS_MODULE,
89 .release = gk20a_dbg_gpu_dev_release,
90 .open = gk20a_prof_gpu_dev_open,
91 .unlocked_ioctl = gk20a_dbg_gpu_dev_ioctl,
92#ifdef CONFIG_COMPAT
93 .compat_ioctl = gk20a_dbg_gpu_dev_ioctl,
94#endif
95};
96
97static const struct file_operations gk20a_tsg_ops = {
98 .owner = THIS_MODULE,
99 .release = nvgpu_ioctl_tsg_dev_release,
100 .open = nvgpu_ioctl_tsg_dev_open,
101#ifdef CONFIG_COMPAT
102 .compat_ioctl = nvgpu_ioctl_tsg_dev_ioctl,
103#endif
104 .unlocked_ioctl = nvgpu_ioctl_tsg_dev_ioctl,
105};
106
107#ifdef CONFIG_GK20A_CTXSW_TRACE
108static const struct file_operations gk20a_ctxsw_ops = {
109 .owner = THIS_MODULE,
110 .release = gk20a_ctxsw_dev_release,
111 .open = gk20a_ctxsw_dev_open,
112#ifdef CONFIG_COMPAT
113 .compat_ioctl = gk20a_ctxsw_dev_ioctl,
114#endif
115 .unlocked_ioctl = gk20a_ctxsw_dev_ioctl,
116 .poll = gk20a_ctxsw_dev_poll,
117 .read = gk20a_ctxsw_dev_read,
118 .mmap = gk20a_ctxsw_dev_mmap,
119};
120#endif
121
122static const struct file_operations gk20a_sched_ops = {
123 .owner = THIS_MODULE,
124 .release = gk20a_sched_dev_release,
125 .open = gk20a_sched_dev_open,
126#ifdef CONFIG_COMPAT
127 .compat_ioctl = gk20a_sched_dev_ioctl,
128#endif
129 .unlocked_ioctl = gk20a_sched_dev_ioctl,
130 .poll = gk20a_sched_dev_poll,
131 .read = gk20a_sched_dev_read,
132};
133
134static int gk20a_create_device(
135 struct device *dev, int devno,
136 const char *interface_name, const char *cdev_name,
137 struct cdev *cdev, struct device **out,
138 const struct file_operations *ops,
139 struct class *class)
140{
141 struct device *subdev;
142 int err;
143 struct gk20a *g = gk20a_from_dev(dev);
144
145 nvgpu_log_fn(g, " ");
146
147 cdev_init(cdev, ops);
148 cdev->owner = THIS_MODULE;
149
150 err = cdev_add(cdev, devno, 1);
151 if (err) {
152 dev_err(dev, "failed to add %s cdev\n", cdev_name);
153 return err;
154 }
155
156 subdev = device_create(class, NULL, devno, NULL,
157 interface_name, cdev_name);
158
159 if (IS_ERR(subdev)) {
160 err = PTR_ERR(dev);
161 cdev_del(cdev);
162 dev_err(dev, "failed to create %s device for %s\n",
163 cdev_name, dev_name(dev));
164 return err;
165 }
166
167 *out = subdev;
168 return 0;
169}
170
171void gk20a_user_deinit(struct device *dev, struct class *class)
172{
173 struct gk20a *g = gk20a_from_dev(dev);
174 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
175
176 if (l->channel.node) {
177 device_destroy(class, l->channel.cdev.dev);
178 cdev_del(&l->channel.cdev);
179 }
180
181 if (l->as_dev.node) {
182 device_destroy(class, l->as_dev.cdev.dev);
183 cdev_del(&l->as_dev.cdev);
184 }
185
186 if (l->ctrl.node) {
187 device_destroy(class, l->ctrl.cdev.dev);
188 cdev_del(&l->ctrl.cdev);
189 }
190
191 if (l->dbg.node) {
192 device_destroy(class, l->dbg.cdev.dev);
193 cdev_del(&l->dbg.cdev);
194 }
195
196 if (l->prof.node) {
197 device_destroy(class, l->prof.cdev.dev);
198 cdev_del(&l->prof.cdev);
199 }
200
201 if (l->tsg.node) {
202 device_destroy(class, l->tsg.cdev.dev);
203 cdev_del(&l->tsg.cdev);
204 }
205
206 if (l->ctxsw.node) {
207 device_destroy(class, l->ctxsw.cdev.dev);
208 cdev_del(&l->ctxsw.cdev);
209 }
210
211 if (l->sched.node) {
212 device_destroy(class, l->sched.cdev.dev);
213 cdev_del(&l->sched.cdev);
214 }
215
216 if (l->cdev_region)
217 unregister_chrdev_region(l->cdev_region, GK20A_NUM_CDEVS);
218}
219
220int gk20a_user_init(struct device *dev, const char *interface_name,
221 struct class *class)
222{
223 int err;
224 dev_t devno;
225 struct gk20a *g = gk20a_from_dev(dev);
226 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
227
228 err = alloc_chrdev_region(&devno, 0, GK20A_NUM_CDEVS, dev_name(dev));
229 if (err) {
230 dev_err(dev, "failed to allocate devno\n");
231 goto fail;
232 }
233 l->cdev_region = devno;
234
235 err = gk20a_create_device(dev, devno++, interface_name, "",
236 &l->channel.cdev, &l->channel.node,
237 &gk20a_channel_ops,
238 class);
239 if (err)
240 goto fail;
241
242 err = gk20a_create_device(dev, devno++, interface_name, "-as",
243 &l->as_dev.cdev, &l->as_dev.node,
244 &gk20a_as_ops,
245 class);
246 if (err)
247 goto fail;
248
249 err = gk20a_create_device(dev, devno++, interface_name, "-ctrl",
250 &l->ctrl.cdev, &l->ctrl.node,
251 &gk20a_ctrl_ops,
252 class);
253 if (err)
254 goto fail;
255
256 err = gk20a_create_device(dev, devno++, interface_name, "-dbg",
257 &l->dbg.cdev, &l->dbg.node,
258 &gk20a_dbg_ops,
259 class);
260 if (err)
261 goto fail;
262
263 err = gk20a_create_device(dev, devno++, interface_name, "-prof",
264 &l->prof.cdev, &l->prof.node,
265 &gk20a_prof_ops,
266 class);
267 if (err)
268 goto fail;
269
270 err = gk20a_create_device(dev, devno++, interface_name, "-tsg",
271 &l->tsg.cdev, &l->tsg.node,
272 &gk20a_tsg_ops,
273 class);
274 if (err)
275 goto fail;
276
277#if defined(CONFIG_GK20A_CTXSW_TRACE)
278 err = gk20a_create_device(dev, devno++, interface_name, "-ctxsw",
279 &l->ctxsw.cdev, &l->ctxsw.node,
280 &gk20a_ctxsw_ops,
281 class);
282 if (err)
283 goto fail;
284#endif
285
286 err = gk20a_create_device(dev, devno++, interface_name, "-sched",
287 &l->sched.cdev, &l->sched.node,
288 &gk20a_sched_ops,
289 class);
290 if (err)
291 goto fail;
292
293 return 0;
294fail:
295 gk20a_user_deinit(dev, &nvgpu_class);
296 return err;
297}
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-30 18:16:11 -0400