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-rw-r--r--include/os/linux/io.c130
1 files changed, 130 insertions, 0 deletions
diff --git a/include/os/linux/io.c b/include/os/linux/io.c
new file mode 100644
index 0000000..3e84e88
--- /dev/null
+++ b/include/os/linux/io.c
@@ -0,0 +1,130 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#include <nvgpu/io.h>
15#include <nvgpu/types.h>
16#include <nvgpu/gk20a.h>
17
18#include "os_linux.h"
19
20void nvgpu_writel(struct gk20a *g, u32 r, u32 v)
21{
22 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
23
24 if (unlikely(!l->regs)) {
25 __gk20a_warn_on_no_regs();
26 nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v);
27 } else {
28 writel_relaxed(v, l->regs + r);
29 nvgpu_wmb();
30 nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x", r, v);
31 }
32}
33
34void nvgpu_writel_relaxed(struct gk20a *g, u32 r, u32 v)
35{
36 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
37
38 if (unlikely(!l->regs)) {
39 __gk20a_warn_on_no_regs();
40 nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v);
41 } else {
42 writel_relaxed(v, l->regs + r);
43 }
44}
45
46u32 nvgpu_readl(struct gk20a *g, u32 r)
47{
48 u32 v = __nvgpu_readl(g, r);
49
50 if (v == 0xffffffff)
51 __nvgpu_check_gpu_state(g);
52
53 return v;
54}
55
56u32 __nvgpu_readl(struct gk20a *g, u32 r)
57{
58 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
59 u32 v = 0xffffffff;
60
61 if (unlikely(!l->regs)) {
62 __gk20a_warn_on_no_regs();
63 nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v);
64 } else {
65 v = readl(l->regs + r);
66 nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x", r, v);
67 }
68
69 return v;
70}
71
72void nvgpu_writel_loop(struct gk20a *g, u32 r, u32 v)
73{
74 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
75
76 if (unlikely(!l->regs)) {
77 __gk20a_warn_on_no_regs();
78 nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v);
79 } else {
80 nvgpu_wmb();
81 do {
82 writel_relaxed(v, l->regs + r);
83 } while (readl(l->regs + r) != v);
84 nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x", r, v);
85 }
86}
87
88void nvgpu_bar1_writel(struct gk20a *g, u32 b, u32 v)
89{
90 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
91
92 if (unlikely(!l->bar1)) {
93 __gk20a_warn_on_no_regs();
94 nvgpu_log(g, gpu_dbg_reg, "b=0x%x v=0x%x (failed)", b, v);
95 } else {
96 nvgpu_wmb();
97 writel_relaxed(v, l->bar1 + b);
98 nvgpu_log(g, gpu_dbg_reg, "b=0x%x v=0x%x", b, v);
99 }
100}
101
102u32 nvgpu_bar1_readl(struct gk20a *g, u32 b)
103{
104 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
105 u32 v = 0xffffffff;
106
107 if (unlikely(!l->bar1)) {
108 __gk20a_warn_on_no_regs();
109 nvgpu_log(g, gpu_dbg_reg, "b=0x%x v=0x%x (failed)", b, v);
110 } else {
111 v = readl(l->bar1 + b);
112 nvgpu_log(g, gpu_dbg_reg, "b=0x%x v=0x%x", b, v);
113 }
114
115 return v;
116}
117
118bool nvgpu_io_exists(struct gk20a *g)
119{
120 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
121
122 return l->regs != NULL;
123}
124
125bool nvgpu_io_valid_reg(struct gk20a *g, u32 r)
126{
127 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
128
129 return r < resource_size(l->regs);
130}