diff options
Diffstat (limited to 'include/os/linux/intr.c')
-rw-r--r-- | include/os/linux/intr.c | 136 |
1 files changed, 0 insertions, 136 deletions
diff --git a/include/os/linux/intr.c b/include/os/linux/intr.c deleted file mode 100644 index 8838b72..0000000 --- a/include/os/linux/intr.c +++ /dev/null | |||
@@ -1,136 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #include <trace/events/gk20a.h> | ||
15 | #include <linux/irqreturn.h> | ||
16 | |||
17 | #include <nvgpu/gk20a.h> | ||
18 | |||
19 | #include <nvgpu/atomic.h> | ||
20 | #include <nvgpu/unit.h> | ||
21 | #include "os_linux.h" | ||
22 | |||
23 | irqreturn_t nvgpu_intr_stall(struct gk20a *g) | ||
24 | { | ||
25 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | ||
26 | u32 mc_intr_0; | ||
27 | |||
28 | trace_mc_gk20a_intr_stall(g->name); | ||
29 | |||
30 | if (!g->power_on) | ||
31 | return IRQ_NONE; | ||
32 | |||
33 | /* not from gpu when sharing irq with others */ | ||
34 | mc_intr_0 = g->ops.mc.intr_stall(g); | ||
35 | if (unlikely(!mc_intr_0)) | ||
36 | return IRQ_NONE; | ||
37 | |||
38 | g->ops.mc.intr_stall_pause(g); | ||
39 | |||
40 | atomic_inc(&l->hw_irq_stall_count); | ||
41 | |||
42 | trace_mc_gk20a_intr_stall_done(g->name); | ||
43 | |||
44 | return IRQ_WAKE_THREAD; | ||
45 | } | ||
46 | |||
47 | irqreturn_t nvgpu_intr_thread_stall(struct gk20a *g) | ||
48 | { | ||
49 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | ||
50 | int hw_irq_count; | ||
51 | |||
52 | nvgpu_log(g, gpu_dbg_intr, "interrupt thread launched"); | ||
53 | |||
54 | trace_mc_gk20a_intr_thread_stall(g->name); | ||
55 | |||
56 | hw_irq_count = atomic_read(&l->hw_irq_stall_count); | ||
57 | g->ops.mc.isr_stall(g); | ||
58 | g->ops.mc.intr_stall_resume(g); | ||
59 | /* sync handled irq counter before re-enabling interrupts */ | ||
60 | atomic_set(&l->sw_irq_stall_last_handled, hw_irq_count); | ||
61 | |||
62 | nvgpu_cond_broadcast(&l->sw_irq_stall_last_handled_wq); | ||
63 | |||
64 | trace_mc_gk20a_intr_thread_stall_done(g->name); | ||
65 | |||
66 | return IRQ_HANDLED; | ||
67 | } | ||
68 | |||
69 | irqreturn_t nvgpu_intr_nonstall(struct gk20a *g) | ||
70 | { | ||
71 | u32 non_stall_intr_val; | ||
72 | u32 hw_irq_count; | ||
73 | int ops_old, ops_new, ops = 0; | ||
74 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | ||
75 | |||
76 | if (!g->power_on) | ||
77 | return IRQ_NONE; | ||
78 | |||
79 | /* not from gpu when sharing irq with others */ | ||
80 | non_stall_intr_val = g->ops.mc.intr_nonstall(g); | ||
81 | if (unlikely(!non_stall_intr_val)) | ||
82 | return IRQ_NONE; | ||
83 | |||
84 | g->ops.mc.intr_nonstall_pause(g); | ||
85 | |||
86 | ops = g->ops.mc.isr_nonstall(g); | ||
87 | if (ops) { | ||
88 | do { | ||
89 | ops_old = atomic_read(&l->nonstall_ops); | ||
90 | ops_new = ops_old | ops; | ||
91 | } while (ops_old != atomic_cmpxchg(&l->nonstall_ops, | ||
92 | ops_old, ops_new)); | ||
93 | |||
94 | queue_work(l->nonstall_work_queue, &l->nonstall_fn_work); | ||
95 | } | ||
96 | |||
97 | hw_irq_count = atomic_inc_return(&l->hw_irq_nonstall_count); | ||
98 | |||
99 | /* sync handled irq counter before re-enabling interrupts */ | ||
100 | atomic_set(&l->sw_irq_nonstall_last_handled, hw_irq_count); | ||
101 | |||
102 | g->ops.mc.intr_nonstall_resume(g); | ||
103 | |||
104 | nvgpu_cond_broadcast(&l->sw_irq_nonstall_last_handled_wq); | ||
105 | |||
106 | return IRQ_HANDLED; | ||
107 | } | ||
108 | |||
109 | static void mc_gk20a_handle_intr_nonstall(struct gk20a *g, u32 ops) | ||
110 | { | ||
111 | bool semaphore_wakeup, post_events; | ||
112 | |||
113 | semaphore_wakeup = | ||
114 | (((ops & GK20A_NONSTALL_OPS_WAKEUP_SEMAPHORE) != 0U) ? | ||
115 | true : false); | ||
116 | post_events = (((ops & GK20A_NONSTALL_OPS_POST_EVENTS) != 0U) ? | ||
117 | true: false); | ||
118 | |||
119 | if (semaphore_wakeup) { | ||
120 | g->ops.semaphore_wakeup(g, post_events); | ||
121 | } | ||
122 | } | ||
123 | |||
124 | void nvgpu_intr_nonstall_cb(struct work_struct *work) | ||
125 | { | ||
126 | struct nvgpu_os_linux *l = | ||
127 | container_of(work, struct nvgpu_os_linux, nonstall_fn_work); | ||
128 | struct gk20a *g = &l->g; | ||
129 | |||
130 | do { | ||
131 | u32 ops; | ||
132 | |||
133 | ops = atomic_xchg(&l->nonstall_ops, 0); | ||
134 | mc_gk20a_handle_intr_nonstall(g, ops); | ||
135 | } while (atomic_read(&l->nonstall_ops) != 0); | ||
136 | } | ||