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-rw-r--r--include/os/linux/driver_common.c400
1 files changed, 0 insertions, 400 deletions
diff --git a/include/os/linux/driver_common.c b/include/os/linux/driver_common.c
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index 8f5872d..0000000
--- a/include/os/linux/driver_common.c
+++ /dev/null
@@ -1,400 +0,0 @@
1/*
2 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/reboot.h>
18#include <linux/dma-mapping.h>
19#include <linux/mm.h>
20#include <linux/slab.h>
21#include <linux/of_platform.h>
22#include <uapi/linux/nvgpu.h>
23
24#include <nvgpu/defaults.h>
25#include <nvgpu/kmem.h>
26#include <nvgpu/nvgpu_common.h>
27#include <nvgpu/soc.h>
28#include <nvgpu/bug.h>
29#include <nvgpu/enabled.h>
30#include <nvgpu/debug.h>
31#include <nvgpu/sizes.h>
32#include <nvgpu/gk20a.h>
33
34#include "platform_gk20a.h"
35#include "module.h"
36#include "os_linux.h"
37#include "sysfs.h"
38#include "ioctl.h"
39#include "gk20a/regops_gk20a.h"
40
41#define EMC3D_DEFAULT_RATIO 750
42
43void nvgpu_kernel_restart(void *cmd)
44{
45 kernel_restart(cmd);
46}
47
48static void nvgpu_init_vars(struct gk20a *g)
49{
50 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
51 struct device *dev = dev_from_gk20a(g);
52 struct gk20a_platform *platform = dev_get_drvdata(dev);
53
54 nvgpu_cond_init(&l->sw_irq_stall_last_handled_wq);
55 nvgpu_cond_init(&l->sw_irq_nonstall_last_handled_wq);
56
57 init_rwsem(&l->busy_lock);
58 nvgpu_rwsem_init(&g->deterministic_busy);
59
60 nvgpu_spinlock_init(&g->mc_enable_lock);
61
62 nvgpu_mutex_init(&platform->railgate_lock);
63 nvgpu_mutex_init(&g->dbg_sessions_lock);
64 nvgpu_mutex_init(&g->client_lock);
65 nvgpu_mutex_init(&g->power_lock);
66 nvgpu_mutex_init(&g->ctxsw_disable_lock);
67 nvgpu_mutex_init(&g->tpc_pg_lock);
68 nvgpu_mutex_init(&g->clk_arb_enable_lock);
69 nvgpu_mutex_init(&g->cg_pg_lock);
70
71 /* Init the clock req count to 0 */
72 nvgpu_atomic_set(&g->clk_arb_global_nr, 0);
73
74 nvgpu_mutex_init(&l->ctrl.privs_lock);
75 nvgpu_init_list_node(&l->ctrl.privs);
76
77 l->regs_saved = l->regs;
78 l->bar1_saved = l->bar1;
79
80 g->emc3d_ratio = EMC3D_DEFAULT_RATIO;
81
82 /* Set DMA parameters to allow larger sgt lists */
83 dev->dma_parms = &l->dma_parms;
84 dma_set_max_seg_size(dev, UINT_MAX);
85
86 /*
87 * A default of 16GB is the largest supported DMA size that is
88 * acceptable to all currently supported Tegra SoCs.
89 */
90 if (!platform->dma_mask)
91 platform->dma_mask = DMA_BIT_MASK(34);
92
93 dma_set_mask(dev, platform->dma_mask);
94 dma_set_coherent_mask(dev, platform->dma_mask);
95
96 nvgpu_init_list_node(&g->profiler_objects);
97
98 nvgpu_init_list_node(&g->boardobj_head);
99 nvgpu_init_list_node(&g->boardobjgrp_head);
100
101 __nvgpu_set_enabled(g, NVGPU_HAS_SYNCPOINTS, platform->has_syncpoints);
102}
103
104static void nvgpu_init_gr_vars(struct gk20a *g)
105{
106 gk20a_init_gr(g);
107
108 nvgpu_log_info(g, "total ram pages : %lu", totalram_pages);
109 g->gr.max_comptag_mem = totalram_size_in_mb;
110}
111
112static void nvgpu_init_timeout(struct gk20a *g)
113{
114 struct gk20a_platform *platform = dev_get_drvdata(dev_from_gk20a(g));
115
116 g->timeouts_disabled_by_user = false;
117 nvgpu_atomic_set(&g->timeouts_disabled_refcount, 0);
118
119 if (nvgpu_platform_is_silicon(g)) {
120 g->gr_idle_timeout_default = NVGPU_DEFAULT_GR_IDLE_TIMEOUT;
121 } else if (nvgpu_platform_is_fpga(g)) {
122 g->gr_idle_timeout_default = GK20A_TIMEOUT_FPGA;
123 } else {
124 g->gr_idle_timeout_default = (u32)ULONG_MAX;
125 }
126 g->ch_wdt_timeout_ms = platform->ch_wdt_timeout_ms;
127 g->fifo_eng_timeout_us = GRFIFO_TIMEOUT_CHECK_PERIOD_US;
128}
129
130static void nvgpu_init_timeslice(struct gk20a *g)
131{
132 g->runlist_interleave = true;
133
134 g->timeslice_low_priority_us = 1300;
135 g->timeslice_medium_priority_us = 2600;
136 g->timeslice_high_priority_us = 5200;
137
138 g->min_timeslice_us = 1000;
139 g->max_timeslice_us = 50000;
140}
141
142static void nvgpu_init_pm_vars(struct gk20a *g)
143{
144 struct gk20a_platform *platform = dev_get_drvdata(dev_from_gk20a(g));
145 u32 i = 0;
146
147 /*
148 * Set up initial power settings. For non-slicon platforms, disable
149 * power features and for silicon platforms, read from platform data
150 */
151 g->slcg_enabled =
152 nvgpu_platform_is_silicon(g) ? platform->enable_slcg : false;
153 g->blcg_enabled =
154 nvgpu_platform_is_silicon(g) ? platform->enable_blcg : false;
155 g->elcg_enabled =
156 nvgpu_platform_is_silicon(g) ? platform->enable_elcg : false;
157 g->elpg_enabled =
158 nvgpu_platform_is_silicon(g) ? platform->enable_elpg : false;
159 g->aelpg_enabled =
160 nvgpu_platform_is_silicon(g) ? platform->enable_aelpg : false;
161 g->mscg_enabled =
162 nvgpu_platform_is_silicon(g) ? platform->enable_mscg : false;
163 g->can_elpg =
164 nvgpu_platform_is_silicon(g) ? platform->can_elpg_init : false;
165
166 __nvgpu_set_enabled(g, NVGPU_GPU_CAN_ELCG,
167 nvgpu_platform_is_silicon(g) ? platform->can_elcg : false);
168 __nvgpu_set_enabled(g, NVGPU_GPU_CAN_SLCG,
169 nvgpu_platform_is_silicon(g) ? platform->can_slcg : false);
170 __nvgpu_set_enabled(g, NVGPU_GPU_CAN_BLCG,
171 nvgpu_platform_is_silicon(g) ? platform->can_blcg : false);
172
173 g->aggressive_sync_destroy = platform->aggressive_sync_destroy;
174 g->aggressive_sync_destroy_thresh = platform->aggressive_sync_destroy_thresh;
175#ifdef CONFIG_NVGPU_SUPPORT_CDE
176 g->has_cde = platform->has_cde;
177#endif
178 g->ptimer_src_freq = platform->ptimer_src_freq;
179 g->support_pmu = support_gk20a_pmu(dev_from_gk20a(g));
180 __nvgpu_set_enabled(g, NVGPU_CAN_RAILGATE, platform->can_railgate_init);
181 g->can_tpc_powergate = platform->can_tpc_powergate;
182
183 for (i = 0; i < MAX_TPC_PG_CONFIGS; i++)
184 g->valid_tpc_mask[i] = platform->valid_tpc_mask[i];
185
186 g->ldiv_slowdown_factor = platform->ldiv_slowdown_factor_init;
187 /* if default delay is not set, set default delay to 500msec */
188 if (platform->railgate_delay_init)
189 g->railgate_delay = platform->railgate_delay_init;
190 else
191 g->railgate_delay = NVGPU_DEFAULT_RAILGATE_IDLE_TIMEOUT;
192 __nvgpu_set_enabled(g, NVGPU_PMU_PERFMON, platform->enable_perfmon);
193
194 /* set default values to aelpg parameters */
195 g->pmu.aelpg_param[0] = APCTRL_SAMPLING_PERIOD_PG_DEFAULT_US;
196 g->pmu.aelpg_param[1] = APCTRL_MINIMUM_IDLE_FILTER_DEFAULT_US;
197 g->pmu.aelpg_param[2] = APCTRL_MINIMUM_TARGET_SAVING_DEFAULT_US;
198 g->pmu.aelpg_param[3] = APCTRL_POWER_BREAKEVEN_DEFAULT_US;
199 g->pmu.aelpg_param[4] = APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT;
200
201 __nvgpu_set_enabled(g, NVGPU_SUPPORT_ASPM, !platform->disable_aspm);
202}
203
204static void nvgpu_init_vbios_vars(struct gk20a *g)
205{
206 struct gk20a_platform *platform = dev_get_drvdata(dev_from_gk20a(g));
207
208 __nvgpu_set_enabled(g, NVGPU_PMU_RUN_PREOS, platform->run_preos);
209 g->vbios_min_version = platform->vbios_min_version;
210}
211
212static void nvgpu_init_ltc_vars(struct gk20a *g)
213{
214 struct gk20a_platform *platform = dev_get_drvdata(dev_from_gk20a(g));
215 <