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Diffstat (limited to 'include/os/linux/debug_clk_gm20b.c')
-rw-r--r--include/os/linux/debug_clk_gm20b.c280
1 files changed, 0 insertions, 280 deletions
diff --git a/include/os/linux/debug_clk_gm20b.c b/include/os/linux/debug_clk_gm20b.c
deleted file mode 100644
index b8b95fd..0000000
--- a/include/os/linux/debug_clk_gm20b.c
+++ /dev/null
@@ -1,280 +0,0 @@
1/*
2 * Copyright (C) 2017-2018 NVIDIA Corporation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 */
14
15#include <linux/uaccess.h>
16#include <linux/debugfs.h>
17#include <linux/seq_file.h>
18
19#include <nvgpu/io.h>
20#include <nvgpu/clk_arb.h>
21
22#include "gm20b/clk_gm20b.h"
23#include "os_linux.h"
24#include "platform_gk20a.h"
25
26static int rate_get(void *data, u64 *val)
27{
28 struct gk20a *g = (struct gk20a *)data;
29 struct clk_gk20a *clk = &g->clk;
30
31 *val = (u64)rate_gpc2clk_to_gpu(clk->gpc_pll.freq);
32 return 0;
33}
34static int rate_set(void *data, u64 val)
35{
36 struct gk20a *g = (struct gk20a *)data;
37 if (nvgpu_clk_arb_has_active_req(g))
38 return 0;
39 return g->ops.clk.set_rate(g, CTRL_CLK_DOMAIN_GPCCLK, (u32)val);
40}
41DEFINE_SIMPLE_ATTRIBUTE(rate_fops, rate_get, rate_set, "%llu\n");
42
43static int pll_reg_show(struct seq_file *s, void *data)
44{
45 struct gk20a *g = s->private;
46 struct nvgpu_clk_pll_debug_data d;
47 u32 reg, m, n, pl, f;
48 int err = 0;
49
50 if (g->ops.clk.get_pll_debug_data) {
51 err = g->ops.clk.get_pll_debug_data(g, &d);
52 if (err)
53 return err;
54 } else {
55 return -EINVAL;
56 }
57
58 seq_printf(s, "bypassctrl = %s, ",
59 d.trim_sys_bypassctrl_val ? "bypass" : "vco");
60 seq_printf(s, "sel_vco = %s, ",
61 d.trim_sys_sel_vco_val ? "vco" : "bypass");
62
63 seq_printf(s, "cfg = 0x%x : %s : %s : %s\n", d.trim_sys_gpcpll_cfg_val,
64 d.trim_sys_gpcpll_cfg_enabled ? "enabled" : "disabled",
65 d.trim_sys_gpcpll_cfg_locked ? "locked" : "unlocked",
66 d.trim_sys_gpcpll_cfg_sync_on ? "sync_on" : "sync_off");
67
68 reg = d.trim_sys_gpcpll_coeff_val;
69 m = d.trim_sys_gpcpll_coeff_mdiv;
70 n = d.trim_sys_gpcpll_coeff_ndiv;
71 pl = d.trim_sys_gpcpll_coeff_pldiv;
72 f = g->clk.gpc_pll.clk_in * n / (m * nvgpu_pl_to_div(pl));
73 seq_printf(s, "coef = 0x%x : m = %u : n = %u : pl = %u", reg, m, n, pl);
74 seq_printf(s, " : pll_f(gpu_f) = %u(%u) kHz\n", f, f/2);
75
76 seq_printf(s, "dvfs0 = 0x%x : d = %u : dmax = %u : doffs = %u\n",
77 d.trim_sys_gpcpll_dvfs0_val,
78 d.trim_sys_gpcpll_dvfs0_dfs_coeff,
79 d.trim_sys_gpcpll_dvfs0_dfs_det_max,
80 d.trim_sys_gpcpll_dvfs0_dfs_dc_offset);
81
82 return 0;
83}
84
85static int pll_reg_open(struct inode *inode, struct file *file)
86{
87 return single_open(file, pll_reg_show, inode->i_private);
88}
89
90static const struct file_operations pll_reg_fops = {
91 .open = pll_reg_open,
92 .read = seq_read,
93 .llseek = seq_lseek,
94 .release = single_release,
95};
96
97static int pll_reg_raw_show(struct seq_file *s, void *data)
98{
99 struct gk20a *g = s->private;
100 struct nvgpu_clk_pll_debug_data d;
101 u32 reg;
102 int err = 0;
103
104 if (g->ops.clk.get_pll_debug_data) {
105 err = g->ops.clk.get_pll_debug_data(g, &d);
106 if (err)
107 return err;
108 } else {
109 return -EINVAL;
110 }
111
112 seq_puts(s, "GPCPLL REGISTERS:\n");
113 for (reg = d.trim_sys_gpcpll_cfg_reg;
114 reg < d.trim_sys_gpcpll_dvfs2_reg;
115 reg += sizeof(u32))
116 seq_printf(s, "[0x%02x] = 0x%08x\n", reg, gk20a_readl(g, reg));
117
118 reg = d.trim_bcast_gpcpll_dvfs2_reg;
119 if (reg)
120 seq_printf(s, "[0x%02x] = 0x%08x\n", reg, gk20a_readl(g, reg));
121
122 seq_puts(s, "\nGPC CLK OUT REGISTERS:\n");
123
124 seq_printf(s, "[0x%02x] = 0x%08x\n", d.trim_sys_sel_vco_reg,
125 d.trim_sys_sel_vco_val);
126 seq_printf(s, "[0x%02x] = 0x%08x\n", d.trim_sys_gpc2clk_out_reg,
127 d.trim_sys_gpc2clk_out_val);
128 seq_printf(s, "[0x%02x] = 0x%08x\n", d.trim_sys_bypassctrl_reg,
129 d.trim_sys_bypassctrl_val);
130
131 return 0;
132}
133
134static int pll_reg_raw_open(struct inode *inode, struct file *file)
135{
136 return single_open(file, pll_reg_raw_show, inode->i_private);
137}
138
139static ssize_t pll_reg_raw_write(struct file *file,
140 const char __user *userbuf, size_t count, loff_t *ppos)
141{
142 struct gk20a *g = file->f_path.dentry->d_inode->i_private;
143 char buf[80];
144 u32 reg, val;
145 int err = 0;
146
147 if (sizeof(buf) <= count)
148 return -EINVAL;
149
150 if (copy_from_user(buf, userbuf, count))
151 return -EFAULT;
152
153 /* terminate buffer and trim - white spaces may be appended
154 * at the end when invoked from shell command line */
155 buf[count] = '\0';
156 strim(buf);
157
158 if (sscanf(buf, "[0x%x] = 0x%x", &reg, &val) != 2)
159 return -EINVAL;
160
161 if (g->ops.clk.pll_reg_write(g, reg, val))
162 err = g->ops.clk.pll_reg_write(g, reg, val);
163 else
164 err = -EINVAL;
165
166 return err;
167}
168
169static const struct file_operations pll_reg_raw_fops = {
170 .open = pll_reg_raw_open,
171 .read = seq_read,
172 .write = pll_reg_raw_write,
173 .llseek = seq_lseek,
174 .release = single_release,
175};
176
177static int monitor_get(void *data, u64 *val)
178{
179 struct gk20a *g = (struct gk20a *)data;
180 int err = 0;
181
182 if (g->ops.clk.get_gpcclk_clock_counter)
183 err = g->ops.clk.get_gpcclk_clock_counter(&g->clk, val);
184 else
185 err = -EINVAL;
186
187 return err;
188}
189DEFINE_SIMPLE_ATTRIBUTE(monitor_fops, monitor_get, NULL, "%llu\n");
190
191static int voltage_get(void *data, u64 *val)
192{
193 struct gk20a *g = (struct gk20a *)data;
194 int err = 0;
195
196 if (g->ops.clk.get_voltage)
197 err = g->ops.clk.get_voltage(&g->clk, val);
198 else
199 err = -EINVAL;
200
201 return err;
202}
203DEFINE_SIMPLE_ATTRIBUTE(voltage_fops, voltage_get, NULL, "%llu\n");
204
205static int pll_param_show(struct seq_file *s, void *data)
206{
207 struct pll_parms *gpc_pll_params = gm20b_get_gpc_pll_parms();
208
209 seq_printf(s, "ADC offs = %d uV, ADC slope = %d uV, VCO ctrl = 0x%x\n",
210 gpc_pll_params->uvdet_offs, gpc_pll_params->uvdet_slope,
211 gpc_pll_params->vco_ctrl);
212 return 0;
213}
214
215static int pll_param_open(struct inode *inode, struct file *file)
216{
217 return single_open(file, pll_param_show, inode->i_private);
218}
219
220static const struct file_operations pll_param_fops = {
221 .open = pll_param_open,
222 .read = seq_read,
223 .llseek = seq_lseek,
224 .release = single_release,
225};
226
227int gm20b_clk_init_debugfs(struct gk20a *g)
228{
229 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
230 struct dentry *d;
231
232 if (!l->debugfs)
233 return -EINVAL;
234
235 d = debugfs_create_file(
236 "rate", S_IRUGO|S_IWUSR, l->debugfs, g, &rate_fops);
237 if (!d)
238 goto err_out;
239
240 d = debugfs_create_file(
241 "pll_reg", S_IRUGO, l->debugfs, g, &pll_reg_fops);
242 if (!d)
243 goto err_out;
244
245 d = debugfs_create_file("pll_reg_raw",
246 S_IRUGO, l->debugfs, g, &pll_reg_raw_fops);
247 if (!d)
248 goto err_out;
249
250 d = debugfs_create_file(
251 "monitor", S_IRUGO, l->debugfs, g, &monitor_fops);
252 if (!d)
253 goto err_out;
254
255 d = debugfs_create_file(
256 "voltage", S_IRUGO, l->debugfs, g, &voltage_fops);
257 if (!d)
258 goto err_out;
259
260 d = debugfs_create_file(
261 "pll_param", S_IRUGO, l->debugfs, g, &pll_param_fops);
262 if (!d)
263 goto err_out;
264
265 d = debugfs_create_u32("pll_na_mode", S_IRUGO, l->debugfs,
266 (u32 *)&g->clk.gpc_pll.mode);
267 if (!d)
268 goto err_out;
269
270 d = debugfs_create_u32("fmax2x_at_vmin_safe_t", S_IRUGO,
271 l->debugfs, (u32 *)&g->clk.dvfs_safe_max_freq);
272 if (!d)
273 goto err_out;
274
275 return 0;
276
277err_out:
278 pr_err("%s: Failed to make debugfs node\n", __func__);
279 return -ENOMEM;
280}
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-30 16:23:54 -0400