16 files changed, 523 insertions, 13 deletions

diff --git a/include/nvgpu/acr/nvgpu_acr.h b/include/nvgpu/acr/nvgpu_acr.h
index 7a0143e..cdb7bb8 100644
--- a/include/nvgpu/acr/nvgpu_acr.h
+++ b/include/nvgpu/acr/nvgpu_acr.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -39,7 +39,11 @@ struct hs_acr;
 struct nvgpu_acr;
 
 #define HSBIN_ACR_BL_UCODE_IMAGE "pmu_bl.bin"
+#define GM20B_HSBIN_ACR_PROD_UCODE "nv_acr_ucode_prod.bin"
+#define GM20B_HSBIN_ACR_DBG_UCODE "nv_acr_ucode_dbg.bin"
 #define HSBIN_ACR_UCODE_IMAGE "acr_ucode.bin"
+#define HSBIN_ACR_PROD_UCODE "acr_ucode_prod.bin"
+#define HSBIN_ACR_DBG_UCODE "acr_ucode_dbg.bin"
 #define HSBIN_ACR_AHESASC_PROD_UCODE "acr_ahesasc_prod_ucode.bin"
 #define HSBIN_ACR_ASB_PROD_UCODE "acr_asb_prod_ucode.bin"
 #define HSBIN_ACR_AHESASC_DBG_UCODE "acr_ahesasc_dbg_ucode.bin"
diff --git a/include/nvgpu/bug.h b/include/nvgpu/bug.h
index 3d139b7..82d641b 100644
--- a/include/nvgpu/bug.h
+++ b/include/nvgpu/bug.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -24,6 +24,24 @@
 
 #ifdef __KERNEL__
 #include <linux/bug.h>
+/*
+ * Define an assert macro that code within nvgpu can use.
+ *
+ * The goal of this macro is for debugging but what that means varies from OS
+ * to OS. On Linux wee don't want to BUG() for general driver misbehaving. BUG()
+ * is a very heavy handed tool - in fact there's probably no where within the
+ * nvgpu core code where it makes sense to use a BUG() when running under Linux.
+ *
+ * However, on QNX (and POSIX) BUG() will just kill the current process. This
+ * means we can use it for handling bugs in nvgpu.
+ *
+ * As a result this macro varies depending on platform.
+ */
+#define nvgpu_assert(cond)      ((void) WARN_ON(!(cond)))
+#define nvgpu_do_assert_print(g, fmt, arg...)                           \
+        do {                                                            \
+                nvgpu_err(g, fmt, ##arg);                               \
+        } while (false)
 #elif defined(__NVGPU_POSIX__)
 #include <nvgpu/posix/bug.h>
 #else
diff --git a/include/nvgpu/enabled.h b/include/nvgpu/enabled.h
index ef55dad..51e9358 100644
--- a/include/nvgpu/enabled.h
+++ b/include/nvgpu/enabled.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -85,7 +85,12 @@ struct gk20a;
 #define NVGPU_MM_USE_PHYSICAL_SG                27
 /* WAR for gm20b chips. */
 #define NVGPU_MM_FORCE_128K_PMU_VM              28
-
+/* SW ERRATA to disable L3 alloc Bit of the physical address.
+ * Bit number varies between SOCs.
+ * E.g. 64GB physical RAM support for gv11b requires this SW errata
+ * to be enabled.
+ */
+#define NVGPU_DISABLE_L3_SUPPORT                29
 /*
  * Host flags
  */
diff --git a/include/nvgpu/gk20a.h b/include/nvgpu/gk20a.h
index aa95969..19bfaee 100644
--- a/include/nvgpu/gk20a.h
+++ b/include/nvgpu/gk20a.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * GK20A Graphics
  *
@@ -517,6 +517,7 @@ struct gpu_ops {
                                         u32 *priv_addr_table,
                                         u32 *priv_addr_table_index);
                 u32 (*fecs_ctxsw_mailbox_size)(void);
+                u32 (*gpc0_gpccs_ctxsw_mailbox_size)(void);
                 int (*init_sw_bundle64)(struct gk20a *g);
                 int (*alloc_global_ctx_buffers)(struct gk20a *g);
                 int (*map_global_ctx_buffers)(struct gk20a *g,
@@ -719,7 +720,7 @@ struct gpu_ops {
                                 struct ch_state *ch_state);
                 u32 (*intr_0_error_mask)(struct gk20a *g);
                 int (*is_preempt_pending)(struct gk20a *g, u32 id,
-                        unsigned int id_type);
+                        unsigned int id_type, bool preempt_retries_left);
                 void (*init_pbdma_intr_descs)(struct fifo_gk20a *f);
                 int (*reset_enable_hw)(struct gk20a *g);
                 int (*setup_userd)(struct channel_gk20a *c);
@@ -1079,6 +1080,7 @@ struct gpu_ops {
                 u32 (*pmu_pg_supported_engines_list)(struct gk20a *g);
                 u32 (*pmu_pg_engines_feature_list)(struct gk20a *g,
                         u32 pg_engine_id);
+                int (*pmu_process_pg_event)(struct gk20a *g, void *pmumsg);
                 bool (*pmu_is_lpwr_feature_supported)(struct gk20a *g,
                         u32 feature_id);
                 int (*pmu_lpwr_enable_pg)(struct gk20a *g, bool pstate_lock);
@@ -1793,6 +1795,8 @@ bool gk20a_check_poweron(struct gk20a *g);
 int gk20a_prepare_poweroff(struct gk20a *g);
 int gk20a_finalize_poweron(struct gk20a *g);
 
+int nvgpu_wait_for_stall_interrupts(struct gk20a *g, u32 timeout);
+int nvgpu_wait_for_nonstall_interrupts(struct gk20a *g, u32 timeout);
 void nvgpu_wait_for_deferred_interrupts(struct gk20a *g);
 
 struct gk20a * __must_check gk20a_get(struct gk20a *g);
diff --git a/include/nvgpu/hw/gk20a/hw_gr_gk20a.h b/include/nvgpu/hw/gk20a/hw_gr_gk20a.h
index 826108f..376cc8f 100644
--- a/include/nvgpu/hw/gk20a/hw_gr_gk20a.h
+++ b/include/nvgpu/hw/gk20a/hw_gr_gk20a.h
@@ -1380,6 +1380,10 @@ static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void)
 {
         return 0x00502400U;
 }
+static inline u32 gr_gpc0_gpccs_ctxsw_mailbox__size_1_v(void)
+{
+        return 0x00000010U;
+}
 static inline u32 gr_fecs_ctxsw_idlestate_r(void)
 {
         return 0x00409420U;
@@ -3804,4 +3808,61 @@ static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void)
 {
         return 0x40000000U;
 }
+
+static inline u32 gr_gpc0_gpccs_falcon_irqstat_r(void)
+{
+        return 0x00502008U;
+}
+static inline u32 gr_gpc0_gpccs_falcon_irqmode_r(void)
+{
+        return 0x0050200cU;
+}
+static inline u32 gr_gpc0_gpccs_falcon_irqmask_r(void)
+{
+        return 0x00502018U;
+}
+static inline u32 gr_gpc0_gpccs_falcon_irqdest_r(void)
+{
+        return 0x0050201cU;
+}
+static inline u32 gr_gpc0_gpccs_falcon_debug1_r(void)
+{
+        return 0x00502090U;
+}
+static inline u32 gr_gpc0_gpccs_falcon_debuginfo_r(void)
+{
+        return 0x00502094U;
+}