aboutsummaryrefslogtreecommitdiffstats
path: root/include/nvgpu/vgpu/vgpu.h
diff options
context:
space:
mode:
Diffstat (limited to 'include/nvgpu/vgpu/vgpu.h')
-rw-r--r--include/nvgpu/vgpu/vgpu.h110
1 files changed, 110 insertions, 0 deletions
diff --git a/include/nvgpu/vgpu/vgpu.h b/include/nvgpu/vgpu/vgpu.h
new file mode 100644
index 0000000..ecdb896
--- /dev/null
+++ b/include/nvgpu/vgpu/vgpu.h
@@ -0,0 +1,110 @@
1/*
2 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __VGPU_COMMON_H__
24#define __VGPU_COMMON_H__
25
26#include <nvgpu/types.h>
27#include <nvgpu/thread.h>
28#include <nvgpu/log.h>
29#include <nvgpu/lock.h>
30#include <nvgpu/vgpu/tegra_vgpu.h>
31
32struct device;
33struct tegra_vgpu_gr_intr_info;
34struct tegra_vgpu_fifo_intr_info;
35struct tegra_vgpu_cmd_msg;
36struct nvgpu_mem;
37struct gk20a;
38struct vm_gk20a;
39struct nvgpu_gr_ctx;
40struct nvgpu_cpu_time_correlation_sample;
41struct vgpu_ecc_stat;
42struct channel_gk20a;
43
44struct vgpu_priv_data {
45 u64 virt_handle;
46 struct nvgpu_thread intr_handler;
47 struct tegra_vgpu_constants_params constants;
48 struct vgpu_ecc_stat *ecc_stats;
49 int ecc_stats_count;
50 u32 num_freqs;
51 unsigned long *freqs;
52 struct nvgpu_mutex vgpu_clk_get_freq_lock;
53};
54
55struct vgpu_priv_data *vgpu_get_priv_data(struct gk20a *g);
56
57static inline u64 vgpu_get_handle(struct gk20a *g)
58{
59 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
60
61 if (unlikely(!priv)) {
62 nvgpu_err(g, "invalid vgpu_priv_data in %s", __func__);
63 return INT_MAX;
64 }
65
66 return priv->virt_handle;
67}
68
69int vgpu_comm_init(struct gk20a *g);
70void vgpu_comm_deinit(void);
71int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in,
72 size_t size_out);
73u64 vgpu_connect(void);
74int vgpu_get_attribute(u64 handle, u32 attrib, u32 *value);
75int vgpu_intr_thread(void *dev_id);
76void vgpu_remove_support_common(struct gk20a *g);
77void vgpu_detect_chip(struct gk20a *g);
78int vgpu_init_gpu_characteristics(struct gk20a *g);
79int vgpu_read_ptimer(struct gk20a *g, u64 *value);
80int vgpu_get_timestamps_zipper(struct gk20a *g,
81 u32 source_id, u32 count,
82 struct nvgpu_cpu_time_correlation_sample *samples);
83int vgpu_init_hal(struct gk20a *g);
84int vgpu_get_constants(struct gk20a *g);
85u64 vgpu_bar1_map(struct gk20a *g, struct nvgpu_mem *mem);
86int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info);
87int vgpu_gr_alloc_gr_ctx(struct gk20a *g,
88 struct nvgpu_gr_ctx *gr_ctx,
89 struct vm_gk20a *vm,
90 u32 class,
91 u32 flags);
92void vgpu_gr_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm,
93 struct nvgpu_gr_ctx *gr_ctx);
94void vgpu_gr_handle_sm_esr_event(struct gk20a *g,
95 struct tegra_vgpu_sm_esr_info *info);
96int vgpu_gr_init_ctx_state(struct gk20a *g);
97int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info);
98u32 vgpu_ce_get_num_pce(struct gk20a *g);
99int vgpu_init_mm_support(struct gk20a *g);
100int vgpu_init_gr_support(struct gk20a *g);
101int vgpu_init_fifo_support(struct gk20a *g);
102
103int vgpu_gp10b_init_hal(struct gk20a *g);
104int vgpu_gv11b_init_hal(struct gk20a *g);
105
106bool vgpu_is_reduced_bar1(struct gk20a *g);
107
108int vgpu_gr_set_mmu_debug_mode(struct gk20a *g,
109 struct channel_gk20a *ch, bool enable);
110#endif