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diff --git a/include/nvgpu/semaphore.h b/include/nvgpu/semaphore.h
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1/*
2 * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef SEMAPHORE_GK20A_H
24#define SEMAPHORE_GK20A_H
25
26#include <nvgpu/log.h>
27#include <nvgpu/atomic.h>
28#include <nvgpu/kref.h>
29#include <nvgpu/list.h>
30#include <nvgpu/nvgpu_mem.h>
31
32#include "gk20a/mm_gk20a.h"
33
34struct gk20a;
35
36#define gpu_sema_dbg(g, fmt, args...) \
37 nvgpu_log(g, gpu_dbg_sema, fmt, ##args)
38#define gpu_sema_verbose_dbg(g, fmt, args...) \
39 nvgpu_log(g, gpu_dbg_sema_v, fmt, ##args)
40
41/*
42 * Max number of channels that can be used is 512. This of course needs to be
43 * fixed to be dynamic but still fast.
44 */
45#define SEMAPHORE_POOL_COUNT 512U
46#define SEMAPHORE_SIZE 16U
47#define SEMAPHORE_SEA_GROWTH_RATE 32U
48
49struct nvgpu_semaphore_sea;
50
51struct nvgpu_semaphore_loc {
52 struct nvgpu_semaphore_pool *pool; /* Pool that owns this sema. */
53 u32 offset; /* Byte offset into the pool. */
54};
55
56/*
57 * Underlying semaphore data structure. This semaphore can be shared amongst
58 * other semaphore instances.
59 */
60struct nvgpu_semaphore_int {
61 struct nvgpu_semaphore_loc location;
62 nvgpu_atomic_t next_value; /* Next available value. */
63 struct channel_gk20a *ch; /* Channel that owns this sema. */
64};
65
66/*
67 * A semaphore which the rest of the driver actually uses. This consists of a
68 * pointer to a real semaphore and a value to wait for. This allows one physical
69 * semaphore to be shared among an essentially infinite number of submits.
70 */
71struct nvgpu_semaphore {
72 struct gk20a *g;
73 struct nvgpu_semaphore_loc location;
74
75 nvgpu_atomic_t value;
76 bool incremented;
77
78 struct nvgpu_ref ref;
79};
80
81/*
82 * A semaphore pool. Each address space will own exactly one of these.
83 */
84struct nvgpu_semaphore_pool {
85 struct nvgpu_list_node pool_list_entry; /* Node for list of pools. */
86 u64 gpu_va; /* GPU access to the pool. */
87 u64 gpu_va_ro; /* GPU access to the pool. */
88 u64 page_idx; /* Index into sea bitmap. */
89
90 DECLARE_BITMAP(semas_alloced, PAGE_SIZE / SEMAPHORE_SIZE);
91
92 struct nvgpu_semaphore_sea *sema_sea; /* Sea that owns this pool. */
93
94 struct nvgpu_mutex pool_lock;
95
96 /*
97 * This is the address spaces's personal RW table. Other channels will
98 * ultimately map this page as RO. This is a sub-nvgpu_mem from the
99 * sea's mem.
100 */
101 struct nvgpu_mem rw_mem;
102
103 bool mapped;
104
105 /*
106 * Sometimes a channel can be released before other channels are
107 * done waiting on it. This ref count ensures that the pool doesn't
108 * go away until all semaphores using this pool are cleaned up first.
109 */
110 struct nvgpu_ref ref;
111};
112
113static inline struct nvgpu_semaphore_pool *
114nvgpu_semaphore_pool_from_pool_list_entry(struct nvgpu_list_node *node)
115{
116 return (struct nvgpu_semaphore_pool *)
117 ((uintptr_t)node -
118 offsetof(struct nvgpu_semaphore_pool, pool_list_entry));
119};
120
121/*
122 * A sea of semaphores pools. Each pool is owned by a single VM. Since multiple
123 * channels can share a VM each channel gets it's own HW semaphore from the
124 * pool. Channels then allocate regular semaphores - basically just a value that
125 * signifies when a particular job is done.
126 */
127struct nvgpu_semaphore_sea {
128 struct nvgpu_list_node pool_list; /* List of pools in this sea. */
129 struct gk20a *gk20a;
130
131 size_t size; /* Number of pages available. */
132 u64 gpu_va; /* GPU virtual address of sema sea. */
133 u64 map_size; /* Size of the mapping. */
134
135 /*
136 * TODO:
137 * List of pages that we use to back the pools. The number of pages
138 * can grow dynamically since allocating 512 pages for all channels at
139 * once would be a tremendous waste.
140 */
141 int page_count; /* Pages allocated to pools. */
142
143 /*
144 * The read-only memory for the entire semaphore sea. Each semaphore
145 * pool needs a sub-nvgpu_mem that will be mapped as RW in its address
146 * space. This sea_mem cannot be freed until all semaphore_pools have
147 * been freed.
148 */
149 struct nvgpu_mem sea_mem;
150
151 /*
152 * Can't use a regular allocator here since the full range of pools are
153 * not always allocated. Instead just use a bitmap.
154 */
155 DECLARE_BITMAP(pools_alloced, SEMAPHORE_POOL_COUNT);
156
157 struct nvgpu_mutex sea_lock; /* Lock alloc/free calls. */
158};
159
160/*
161 * Semaphore sea functions.
162 */
163struct nvgpu_semaphore_sea *nvgpu_semaphore_sea_create(struct gk20a *gk20a);
164void nvgpu_semaphore_sea_destroy(struct gk20a *g);
165int nvgpu_semaphore_sea_map(struct nvgpu_semaphore_pool *sea,
166 struct vm_gk20a *vm);
167void nvgpu_semaphore_sea_unmap(struct nvgpu_semaphore_pool *sea,
168 struct vm_gk20a *vm);
169struct nvgpu_semaphore_sea *nvgpu_semaphore_get_sea(struct gk20a *g);
170
171/*
172 * Semaphore pool functions.
173 */
174int nvgpu_semaphore_pool_alloc(struct nvgpu_semaphore_sea *sea,
175 struct nvgpu_semaphore_pool **pool);
176int nvgpu_semaphore_pool_map(struct nvgpu_semaphore_pool *pool,
177 struct vm_gk20a *vm);
178void nvgpu_semaphore_pool_unmap(struct nvgpu_semaphore_pool *pool,
179 struct vm_gk20a *vm);
180u64 __nvgpu_semaphore_pool_gpu_va(struct nvgpu_semaphore_pool *p, bool global);
181void nvgpu_semaphore_pool_get(struct nvgpu_semaphore_pool *p);
182void nvgpu_semaphore_pool_put(struct nvgpu_semaphore_pool *p);
183
184/*
185 * Semaphore functions.
186 */
187struct nvgpu_semaphore *nvgpu_semaphore_alloc(struct channel_gk20a *ch);
188void nvgpu_semaphore_put(struct nvgpu_semaphore *s);
189void nvgpu_semaphore_get(struct nvgpu_semaphore *s);
190void nvgpu_semaphore_free_hw_sema(struct channel_gk20a *ch);
191
192u64 nvgpu_semaphore_gpu_rw_va(struct nvgpu_semaphore *s);
193u64 nvgpu_semaphore_gpu_ro_va(struct nvgpu_semaphore *s);
194u64 nvgpu_hw_sema_addr(struct nvgpu_semaphore_int *hw_sema);
195
196u32 __nvgpu_semaphore_read(struct nvgpu_semaphore_int *hw_sema);
197u32 nvgpu_semaphore_read(struct nvgpu_semaphore *s);
198u32 nvgpu_semaphore_get_value(struct nvgpu_semaphore *s);
199bool nvgpu_semaphore_is_released(struct nvgpu_semaphore *s);
200bool nvgpu_semaphore_is_acquired(struct nvgpu_semaphore *s);
201
202bool nvgpu_semaphore_reset(struct nvgpu_semaphore_int *hw_sema);
203void nvgpu_semaphore_prepare(struct nvgpu_semaphore *s,
204 struct nvgpu_semaphore_int *hw_sema);
205
206#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-30 18:11:13 -0400