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-rw-r--r--include/nvgpu/pmuif/gpmuifvolt.h402
1 files changed, 402 insertions, 0 deletions
diff --git a/include/nvgpu/pmuif/gpmuifvolt.h b/include/nvgpu/pmuif/gpmuifvolt.h
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1/*
2* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3*
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21*/
22#ifndef NVGPU_PMUIF_GPMUIFVOLT_H
23#define NVGPU_PMUIF_GPMUIFVOLT_H
24
25#include "gpmuifboardobj.h"
26#include <nvgpu/flcnif_cmn.h>
27#include "ctrl/ctrlvolt.h"
28
29#define NV_PMU_VOLT_VALUE_0V_IN_UV (0U)
30
31/* ------------- VOLT_RAIL's GRP_SET defines and structures ------------- */
32
33#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_RAIL 0x00U
34#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_DEVICE 0x01U
35#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_POLICY 0x02U
36
37
38struct nv_pmu_volt_volt_rail_boardobjgrp_set_header {
39 struct nv_pmu_boardobjgrp_e32 super;
40};
41
42struct nv_pmu_volt_volt_rail_boardobj_set {
43
44 struct nv_pmu_boardobj super;
45 u8 rel_limit_vfe_equ_idx;
46 u8 alt_rel_limit_vfe_equ_idx;
47 u8 ov_limit_vfe_equ_idx;
48 u8 vmin_limit_vfe_equ_idx;
49 u8 volt_margin_limit_vfe_equ_idx;
50 u8 pwr_equ_idx;
51 u8 volt_dev_idx_default;
52 u8 volt_dev_idx_ipc_vmin;
53 u8 volt_scale_exp_pwr_equ_idx;
54 struct ctrl_boardobjgrp_mask_e32 volt_dev_mask;
55 s32 volt_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES];
56};
57
58union nv_pmu_volt_volt_rail_boardobj_set_union {
59 struct nv_pmu_boardobj board_obj;
60 struct nv_pmu_volt_volt_rail_boardobj_set super;
61};
62
63NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_rail);
64
65/* ------------ VOLT_DEVICE's GRP_SET defines and structures ------------ */
66
67struct nv_pmu_volt_volt_device_boardobjgrp_set_header {
68 struct nv_pmu_boardobjgrp_e32 super;
69};
70
71struct nv_pmu_volt_volt_device_boardobj_set {
72 struct nv_pmu_boardobj super;
73 u32 switch_delay_us;
74 u32 voltage_min_uv;
75 u32 voltage_max_uv;
76 u32 volt_step_uv;
77};
78
79struct nv_pmu_volt_volt_device_vid_boardobj_set {
80 struct nv_pmu_volt_volt_device_boardobj_set super;
81 s32 voltage_base_uv;
82 s32 voltage_offset_scale_uv;
83 u8 gpio_pin[CTRL_VOLT_VOLT_DEV_VID_VSEL_MAX_ENTRIES];
84 u8 vsel_mask;
85};
86
87struct nv_pmu_volt_volt_device_pwm_boardobj_set {
88 struct nv_pmu_volt_volt_device_boardobj_set super;
89 u32 raw_period;
90 s32 voltage_base_uv;
91 s32 voltage_offset_scale_uv;
92 enum nv_pmu_pmgr_pwm_source pwm_source;
93};
94
95union nv_pmu_volt_volt_device_boardobj_set_union {
96 struct nv_pmu_boardobj board_obj;
97 struct nv_pmu_volt_volt_device_boardobj_set super;
98 struct nv_pmu_volt_volt_device_vid_boardobj_set vid;
99 struct nv_pmu_volt_volt_device_pwm_boardobj_set pwm;
100};
101
102NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_device);
103
104/* ------------ VOLT_POLICY's GRP_SET defines and structures ------------ */
105struct nv_pmu_volt_volt_policy_boardobjgrp_set_header {
106 struct nv_pmu_boardobjgrp_e32 super;
107 u8 perf_core_vf_seq_policy_idx;
108};
109
110struct nv_pmu_volt_volt_policy_boardobj_set {
111 struct nv_pmu_boardobj super;
112};
113struct nv_pmu_volt_volt_policy_sr_boardobj_set {
114 struct nv_pmu_volt_volt_policy_boardobj_set super;
115 u8 rail_idx;
116};
117
118struct nv_pmu_volt_volt_policy_sr_multi_step_boardobj_set {
119 struct nv_pmu_volt_volt_policy_sr_boardobj_set super;
120 u16 inter_switch_delay_us;
121 u32 ramp_up_step_size_uv;
122 u32 ramp_down_step_size_uv;
123};
124
125struct nv_pmu_volt_volt_policy_splt_r_boardobj_set {
126 struct nv_pmu_volt_volt_policy_boardobj_set super;
127 u8 rail_idx_master;
128 u8 rail_idx_slave;
129 u8 delta_min_vfe_equ_idx;
130 u8 delta_max_vfe_equ_idx;
131 s32 offset_delta_min_uv;
132 s32 offset_delta_max_uv;
133};
134
135struct nv_pmu_volt_volt_policy_srms_boardobj_set {
136 struct nv_pmu_volt_volt_policy_splt_r_boardobj_set super;
137 u16 inter_switch_delayus;
138};
139
140/* sr - > single_rail */
141struct nv_pmu_volt_volt_policy_srss_boardobj_set {
142 struct nv_pmu_volt_volt_policy_splt_r_boardobj_set super;
143};
144
145union nv_pmu_volt_volt_policy_boardobj_set_union {
146 struct nv_pmu_boardobj board_obj;
147 struct nv_pmu_volt_volt_policy_boardobj_set super;
148 struct nv_pmu_volt_volt_policy_sr_boardobj_set single_rail;
149 struct nv_pmu_volt_volt_policy_sr_multi_step_boardobj_set
150 single_rail_ms;
151 struct nv_pmu_volt_volt_policy_splt_r_boardobj_set split_rail;
152 struct nv_pmu_volt_volt_policy_srms_boardobj_set
153 split_rail_m_s;
154 struct nv_pmu_volt_volt_policy_srss_boardobj_set
155 split_rail_s_s;
156};
157
158NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_policy);
159
160/* ----------- VOLT_RAIL's GRP_GET_STATUS defines and structures ----------- */
161struct nv_pmu_volt_volt_rail_boardobjgrp_get_status_header {
162 struct nv_pmu_boardobjgrp_e32 super;
163};
164
165struct nv_pmu_volt_volt_rail_boardobj_get_status {
166 struct nv_pmu_boardobj_query super;
167 u32 curr_volt_defaultu_v;
168 u32 rel_limitu_v;
169 u32 alt_rel_limitu_v;
170 u32 ov_limitu_v;
171 u32 max_limitu_v;
172 u32 vmin_limitu_v;
173 s32 volt_margin_limitu_v;
174 u32 rsvd;
175};
176
177union nv_pmu_volt_volt_rail_boardobj_get_status_union {
178 struct nv_pmu_boardobj_query board_obj;
179 struct nv_pmu_volt_volt_rail_boardobj_get_status super;
180};
181
182NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(volt, volt_rail);
183
184/* ---------- VOLT_DEVICE's GRP_GET_STATUS defines and structures ---------- */
185struct nv_pmu_volt_volt_device_boardobjgrp_get_status_header {
186 struct nv_pmu_boardobjgrp_e32 super;
187};
188
189struct nv_pmu_volt_volt_device_boardobj_get_status {
190 struct nv_pmu_boardobj_query super;
191};
192
193union nv_pmu_volt_volt_device_boardobj_get_status_union {
194 struct nv_pmu_boardobj_query board_obj;
195 struct nv_pmu_volt_volt_device_boardobj_get_status super;
196};
197
198NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(volt, volt_device);
199
200/* ---------- VOLT_POLICY's GRP_GET_STATUS defines and structures ---------- */
201struct nv_pmu_volt_volt_policy_boardobjgrp_get_status_header {
202 struct nv_pmu_boardobjgrp_e32 super;
203};
204
205struct nv_pmu_volt_volt_policy_boardobj_get_status {
206 struct nv_pmu_boardobj_query super;
207 u32 offset_volt_requ_v;
208 u32 offset_volt_curru_v;
209};
210
211struct nv_pmu_volt_volt_policy_sr_boardobj_get_status {
212 struct nv_pmu_volt_volt_policy_boardobj_get_status super;
213 u32 curr_voltu_v;
214};
215
216struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status {
217 struct nv_pmu_volt_volt_policy_boardobj_get_status super;
218 s32 delta_