1 files changed, 0 insertions, 105 deletions
diff --git a/include/nvgpu/pmuif/gpmuifthermsensor.h b/include/nvgpu/pmuif/gpmuifthermsensor.h
deleted file mode 100644
index 47d35da..0000000
--- a/include/nvgpu/pmuif/gpmuifthermsensor.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
-* Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
-*
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
-*/
-#ifndef NVGPU_PMUIF_GPMUIFTHERMSENSOR_H
-#define NVGPU_PMUIF_GPMUIFTHERMSENSOR_H
-#include "ctrl/ctrltherm.h"
-#include "gpmuifboardobj.h"
-#include <nvgpu/flcnif_cmn.h>
-#define NV_PMU_THERM_BOARDOBJGRP_CLASS_ID_THERM_DEVICE      0x00
-#define NV_PMU_THERM_BOARDOBJGRP_CLASS_ID_THERM_CHANNEL     0x01
-#define NV_PMU_THERM_CMD_ID_BOARDOBJ_GRP_SET                         0x0000000B
-#define NV_PMU_THERM_MSG_ID_BOARDOBJ_GRP_SET                        0x00000008
-struct nv_pmu_therm_therm_device_boardobjgrp_set_header {
-        struct nv_pmu_boardobjgrp_e32 super;
-};
-struct nv_pmu_therm_therm_device_boardobj_set {
-        struct nv_pmu_boardobj super;
-};
-struct nv_pmu_therm_therm_device_gpu_gpc_tsosc_boardobj_set {
-        struct nv_pmu_therm_therm_device_boardobj_set super;
-        u8 gpc_tsosc_idx;
-};
-struct nv_pmu_therm_therm_device_gpu_sci_boardobj_set {
-        struct nv_pmu_therm_therm_device_boardobj_set super;
-};
-struct nv_pmu_therm_therm_device_i2c_boardobj_set {
-        struct nv_pmu_therm_therm_device_boardobj_set super;
-        u8 i2c_dev_idx;
-};
-struct nv_pmu_therm_therm_device_hbm2_site_boardobj_set {
-        struct nv_pmu_therm_therm_device_boardobj_set super;
-        u8 site_idx;
-};
-struct nv_pmu_therm_therm_device_hbm2_combined_boardobj_set {
-        struct nv_pmu_therm_therm_device_boardobj_set super;
-};
-union nv_pmu_therm_therm_device_boardobj_set_union {
-        struct nv_pmu_boardobj board_obj;
-        struct nv_pmu_therm_therm_device_boardobj_set therm_device;
-        struct nv_pmu_therm_therm_device_gpu_gpc_tsosc_boardobj_set gpu_gpc_tsosc;
-        struct nv_pmu_therm_therm_device_gpu_sci_boardobj_set gpu_sci;
-        struct nv_pmu_therm_therm_device_i2c_boardobj_set i2c;
-        struct nv_pmu_therm_therm_device_hbm2_site_boardobj_set hbm2_site;
-        struct nv_pmu_therm_therm_device_hbm2_combined_boardobj_set hbm2_combined;
-};
-NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(therm, therm_device);
-struct nv_pmu_therm_therm_channel_boardobjgrp_set_header {
-        struct nv_pmu_boardobjgrp_e32 super;
-};
-struct nv_pmu_therm_therm_channel_boardobj_set {
-        struct nv_pmu_boardobj super;
-        s16 scaling;
-        s16 offset;
-        s32 temp_min;
-        s32 temp_max;
-};
-struct nv_pmu_therm_therm_channel_device_boardobj_set {
-        struct nv_pmu_therm_therm_channel_boardobj_set super;
-        u8 therm_dev_idx;
-        u8 therm_dev_prov_idx;
-};
-union nv_pmu_therm_therm_channel_boardobj_set_union {
-        struct nv_pmu_boardobj board_obj;
-        struct nv_pmu_therm_therm_channel_boardobj_set therm_channel;
-        struct nv_pmu_therm_therm_channel_device_boardobj_set device;
-};
-NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(therm, therm_channel);
-#endif /* NVGPU_PMUIF_GPMUIFTHERMSENSOR_H */

diff --git a/include/nvgpu/pmuif/gpmuifthermsensor.h b/include/nvgpu/pmuif/gpmuifthermsensor.h deleted file mode 100644 index 47d35da..0000000 --- a/include/nvgpu/pmuif/gpmuifthermsensor.h +++ /dev/null
@@ -1,105 +0,0 @@
1	/*
2	* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:
10	*
11	* The above copyright notice and this permission notice shall be included in
12	* all copies or substantial portions of the Software.
13	*
14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20	* DEALINGS IN THE SOFTWARE.
21	*/
22
23	#ifndef NVGPU_PMUIF_GPMUIFTHERMSENSOR_H
24	#define NVGPU_PMUIF_GPMUIFTHERMSENSOR_H
25
26	#include "ctrl/ctrltherm.h"
27	#include "gpmuifboardobj.h"
28	#include <nvgpu/flcnif_cmn.h>
29
30	#define NV_PMU_THERM_BOARDOBJGRP_CLASS_ID_THERM_DEVICE 0x00
31	#define NV_PMU_THERM_BOARDOBJGRP_CLASS_ID_THERM_CHANNEL 0x01
32
33	#define NV_PMU_THERM_CMD_ID_BOARDOBJ_GRP_SET 0x0000000B
34	#define NV_PMU_THERM_MSG_ID_BOARDOBJ_GRP_SET 0x00000008
35
36	struct nv_pmu_therm_therm_device_boardobjgrp_set_header {
37	struct nv_pmu_boardobjgrp_e32 super;
38	};
39
40	struct nv_pmu_therm_therm_device_boardobj_set {
41	struct nv_pmu_boardobj super;
42	};
43
44	struct nv_pmu_therm_therm_device_gpu_gpc_tsosc_boardobj_set {
45	struct nv_pmu_therm_therm_device_boardobj_set super;
46	u8 gpc_tsosc_idx;
47	};
48
49	struct nv_pmu_therm_therm_device_gpu_sci_boardobj_set {
50	struct nv_pmu_therm_therm_device_boardobj_set super;
51	};
52
53	struct nv_pmu_therm_therm_device_i2c_boardobj_set {
54	struct nv_pmu_therm_therm_device_boardobj_set super;
55	u8 i2c_dev_idx;
56	};
57
58	struct nv_pmu_therm_therm_device_hbm2_site_boardobj_set {
59	struct nv_pmu_therm_therm_device_boardobj_set super;
60	u8 site_idx;
61	};
62
63	struct nv_pmu_therm_therm_device_hbm2_combined_boardobj_set {
64	struct nv_pmu_therm_therm_device_boardobj_set super;
65	};
66
67	union nv_pmu_therm_therm_device_boardobj_set_union {
68	struct nv_pmu_boardobj board_obj;
69	struct nv_pmu_therm_therm_device_boardobj_set therm_device;
70	struct nv_pmu_therm_therm_device_gpu_gpc_tsosc_boardobj_set gpu_gpc_tsosc;
71	struct nv_pmu_therm_therm_device_gpu_sci_boardobj_set gpu_sci;
72	struct nv_pmu_therm_therm_device_i2c_boardobj_set i2c;
73	struct nv_pmu_therm_therm_device_hbm2_site_boardobj_set hbm2_site;
74	struct nv_pmu_therm_therm_device_hbm2_combined_boardobj_set hbm2_combined;
75	};
76
77	NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(therm, therm_device);
78
79	struct nv_pmu_therm_therm_channel_boardobjgrp_set_header {
80	struct nv_pmu_boardobjgrp_e32 super;
81	};
82
83	struct nv_pmu_therm_therm_channel_boardobj_set {
84	struct nv_pmu_boardobj super;
85	s16 scaling;
86	s16 offset;
87	s32 temp_min;
88	s32 temp_max;
89	};
90
91	struct nv_pmu_therm_therm_channel_device_boardobj_set {
92	struct nv_pmu_therm_therm_channel_boardobj_set super;
93	u8 therm_dev_idx;
94	u8 therm_dev_prov_idx;
95	};
96
97	union nv_pmu_therm_therm_channel_boardobj_set_union {
98	struct nv_pmu_boardobj board_obj;
99	struct nv_pmu_therm_therm_channel_boardobj_set therm_channel;
100	struct nv_pmu_therm_therm_channel_device_boardobj_set device;
101	};
102
103	NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(therm, therm_channel);
104
105	#endif /* NVGPU_PMUIF_GPMUIFTHERMSENSOR_H */