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-rw-r--r--include/nvgpu/pmuif/gpmuifperf.h154
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diff --git a/include/nvgpu/pmuif/gpmuifperf.h b/include/nvgpu/pmuif/gpmuifperf.h
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1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22#ifndef NVGPU_PMUIF_GPMUIFPERF_H
23#define NVGPU_PMUIF_GPMUIFPERF_H
24
25#include "gpmuifvolt.h"
26#include "gpmuifperfvfe.h"
27
28/*
29* Enumeration of BOARDOBJGRP class IDs within OBJPERF. Used as "classId"
30* argument for communications between Kernel and PMU via the various generic
31* BOARDOBJGRP interfaces.
32*/
33#define NV_PMU_PERF_BOARDOBJGRP_CLASS_ID_VFE_VAR 0x00U
34#define NV_PMU_PERF_BOARDOBJGRP_CLASS_ID_VFE_EQU 0x01U
35
36#define NV_PMU_PERF_CMD_ID_RPC (0x00000002U)
37#define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_SET (0x00000003U)
38#define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000004U)
39
40/*!
41 * RPC calls serviced by PERF unit.
42 */
43#define NV_PMU_RPC_ID_PERF_BOARD_OBJ_GRP_CMD 0x00U
44#define NV_PMU_RPC_ID_PERF_LOAD 0x01U
45#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_INFO_GET 0x02U
46#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_INFO_SET 0x03U
47#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_SET_CONTROL 0x04U
48#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_QUEUE_CHANGE 0x05U
49#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_LOCK 0x06U
50#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_LOAD 0x07U
51#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_QUERY 0x08U
52#define NV_PMU_RPC_ID_PERF_PERF_LIMITS_INVALIDATE 0x09U
53#define NV_PMU_RPC_ID_PERF_VFE_EQU_EVAL 0x0AU
54#define NV_PMU_RPC_ID_PERF_VFE_INVALIDATE 0x0BU
55#define NV_PMU_RPC_ID_PERF_VFE_EQU_MONITOR_SET 0x0CU
56#define NV_PMU_RPC_ID_PERF_VFE_EQU_MONITOR_GET 0x0DU
57#define NV_PMU_RPC_ID_PERF__COUNT 0x0EU
58/*
59 * Defines the structure that holds data
60 * used to execute LOAD RPC.
61 */
62struct nv_pmu_rpc_struct_perf_load {
63 /*[IN/OUT] Must be first field in RPC structure */
64 struct nv_pmu_rpc_header hdr;
65 u32 scratch[1];
66};
67
68struct nv_pmu_perf_cmd_set_object {
69 u8 cmd_type;
70 u8 pad[2];
71 u8 object_type;
72 struct nv_pmu_allocation object;
73};
74
75#define NV_PMU_PERF_SET_OBJECT_ALLOC_OFFSET \
76 (offsetof(struct nv_pmu_perf_cmd_set_object, object))
77
78/* RPC IDs */
79#define NV_PMU_PERF_RPC_ID_VFE_LOAD (0x00000001U)
80
81/*!
82* Command requesting execution of the perf RPC.
83*/
84struct nv_pmu_perf_cmd_rpc {
85 u8 cmd_type;
86 u8 pad[3];
87 struct nv_pmu_allocation request;
88};
89
90#define NV_PMU_PERF_CMD_RPC_ALLOC_OFFSET \
91 offsetof(struct nv_pmu_perf_cmd_rpc, request)
92
93/*!
94* Simply a union of all specific PERF commands. Forms the general packet
95* exchanged between the Kernel and PMU when sending and receiving PERF commands
96* (respectively).
97*/
98struct nv_pmu_perf_cmd {
99 union {
100 u8 cmd_type;
101 struct nv_pmu_perf_cmd_set_object set_object;
102 struct nv_pmu_boardobj_cmd_grp grp_set;
103 struct nv_pmu_boardobj_cmd_grp grp_get_status;
104 };
105};
106
107/*!
108* Defines the data structure used to invoke PMU perf RPCs. Same structure is
109* used to return the result of the RPC execution.
110*/
111struct nv_pmu_perf_rpc {
112 u8 function;
113 bool b_supported;
114 bool b_success;
115 flcn_status flcn_status;
116 union {
117 struct nv_pmu_perf_rpc_vfe_equ_eval vfe_equ_eval;
118 struct nv_pmu_perf_rpc_vfe_load vfe_load;
119 } params;
120};
121
122
123/* PERF Message-type Definitions */
124#define NV_PMU_PERF_MSG_ID_RPC (0x00000003U)
125#define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_SET (0x00000004U)
126#define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000006U)
127#define NV_PMU_PERF_MSG_ID_VFE_CALLBACK (0x00000005U)
128
129/*!
130* Message carrying the result of the perf RPC execution.
131*/
132struct nv_pmu_perf_msg_rpc {
133 u8 msg_type;
134 u8 rsvd[3];
135 struct nv_pmu_allocation response;
136};
137
138#define NV_PMU_PERF_MSG_RPC_ALLOC_OFFSET \
139 (offsetof(struct nv_pmu_perf_msg_rpc, response))
140
141/*!
142* Simply a union of all specific PERF messages. Forms the general packet
143* exchanged between the Kernel and PMU when sending and receiving PERF messages
144* (respectively).
145*/
146struct nv_pmu_perf_msg {
147 union {
148 u8 msg_type;
149 struct nv_pmu_perf_msg_rpc rpc;
150 struct nv_pmu_boardobj_msg_grp grp_set;
151 };
152};
153
154#endif /* NVGPU_PMUIF_GPMUIFPERF_H*/
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-30 18:13:54 -0400