diff options
Diffstat (limited to 'include/nvgpu/pmuif/gpmuifbios.h')
-rw-r--r-- | include/nvgpu/pmuif/gpmuifbios.h | 50 |
1 files changed, 0 insertions, 50 deletions
diff --git a/include/nvgpu/pmuif/gpmuifbios.h b/include/nvgpu/pmuif/gpmuifbios.h deleted file mode 100644 index e89fbc3..0000000 --- a/include/nvgpu/pmuif/gpmuifbios.h +++ /dev/null | |||
@@ -1,50 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | #ifndef NVGPU_PMUIF_GPMUIFBIOS_H | ||
23 | #define NVGPU_PMUIF_GPMUIFBIOS_H | ||
24 | |||
25 | struct nv_pmu_bios_vfield_register_segment_super { | ||
26 | u8 type; | ||
27 | u8 low_bit; | ||
28 | u8 high_bit; | ||
29 | }; | ||
30 | |||
31 | struct nv_pmu_bios_vfield_register_segment_reg { | ||
32 | struct nv_pmu_bios_vfield_register_segment_super super; | ||
33 | u32 addr; | ||
34 | }; | ||
35 | |||
36 | struct nv_pmu_bios_vfield_register_segment_index_reg { | ||
37 | struct nv_pmu_bios_vfield_register_segment_super super; | ||
38 | u32 addr; | ||
39 | u32 reg_index; | ||
40 | u32 index; | ||
41 | }; | ||
42 | |||
43 | union nv_pmu_bios_vfield_register_segment { | ||
44 | struct nv_pmu_bios_vfield_register_segment_super super; | ||
45 | struct nv_pmu_bios_vfield_register_segment_reg reg; | ||
46 | struct nv_pmu_bios_vfield_register_segment_index_reg index_reg; | ||
47 | }; | ||
48 | |||
49 | |||
50 | #endif /* NVGPU_PMUIF_GPMUIFBIOS_H*/ | ||