diff options
Diffstat (limited to 'include/nvgpu/pmuif/gpmuif_pg.h')
-rw-r--r-- | include/nvgpu/pmuif/gpmuif_pg.h | 412 |
1 files changed, 412 insertions, 0 deletions
diff --git a/include/nvgpu/pmuif/gpmuif_pg.h b/include/nvgpu/pmuif/gpmuif_pg.h new file mode 100644 index 0000000..69a7ea4 --- /dev/null +++ b/include/nvgpu/pmuif/gpmuif_pg.h | |||
@@ -0,0 +1,412 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | #ifndef NVGPU_PMUIF_GPMUIF_PG_H | ||
23 | #define NVGPU_PMUIF_GPMUIF_PG_H | ||
24 | |||
25 | #include "gpmuif_ap.h" | ||
26 | #include "gpmuif_pg_rppg.h" | ||
27 | |||
28 | /*PG defines*/ | ||
29 | |||
30 | /* Identifier for each PG */ | ||
31 | #define PMU_PG_ELPG_ENGINE_ID_GRAPHICS (0x00000000U) | ||
32 | #define PMU_PG_ELPG_ENGINE_ID_MS (0x00000004U) | ||
33 | #define PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE (0x00000005U) | ||
34 | #define PMU_PG_ELPG_ENGINE_MAX PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE | ||
35 | |||
36 | /* PG message */ | ||
37 | enum { | ||
38 | PMU_PG_ELPG_MSG_INIT_ACK, | ||
39 | PMU_PG_ELPG_MSG_DISALLOW_ACK, | ||
40 | PMU_PG_ELPG_MSG_ALLOW_ACK, | ||
41 | PMU_PG_ELPG_MSG_FREEZE_ACK, | ||
42 | PMU_PG_ELPG_MSG_FREEZE_ABORT, | ||
43 | PMU_PG_ELPG_MSG_UNFREEZE_ACK, | ||
44 | }; | ||
45 | |||
46 | struct pmu_pg_msg_elpg_msg { | ||
47 | u8 msg_type; | ||
48 | u8 engine_id; | ||
49 | u16 msg; | ||
50 | }; | ||
51 | |||
52 | enum { | ||
53 | PMU_PG_STAT_MSG_RESP_DMEM_OFFSET = 0, | ||
54 | }; | ||
55 | |||
56 | struct pmu_pg_msg_stat { | ||
57 | u8 msg_type; | ||
58 | u8 engine_id; | ||
59 | u16 sub_msg_id; | ||
60 | u32 data; | ||
61 | }; | ||
62 | |||
63 | enum { | ||
64 | PMU_PG_MSG_ENG_BUF_LOADED, | ||
65 | PMU_PG_MSG_ENG_BUF_UNLOADED, | ||
66 | PMU_PG_MSG_ENG_BUF_FAILED, | ||
67 | }; | ||
68 | |||
69 | struct pmu_pg_msg_eng_buf_stat { | ||
70 | u8 msg_type; | ||
71 | u8 engine_id; | ||
72 | u8 buf_idx; | ||
73 | u8 status; | ||
74 | }; | ||
75 | |||
76 | struct pmu_pg_msg { | ||
77 | union { | ||
78 | u8 msg_type; | ||
79 | struct pmu_pg_msg_elpg_msg elpg_msg; | ||
80 | struct pmu_pg_msg_stat stat; | ||
81 | struct pmu_pg_msg_eng_buf_stat eng_buf_stat; | ||
82 | /* TBD: other pg messages */ | ||
83 | union pmu_ap_msg ap_msg; | ||
84 | struct nv_pmu_rppg_msg rppg_msg; | ||
85 | }; | ||
86 | }; | ||
87 | |||
88 | /* PG commands */ | ||
89 | enum { | ||
90 | PMU_PG_ELPG_CMD_INIT, | ||
91 | PMU_PG_ELPG_CMD_DISALLOW, | ||
92 | PMU_PG_ELPG_CMD_ALLOW, | ||
93 | PMU_PG_ELPG_CMD_FREEZE, | ||
94 | PMU_PG_ELPG_CMD_UNFREEZE, | ||
95 | }; | ||
96 | |||
97 | enum { | ||
98 | PMU_PG_CMD_ID_ELPG_CMD = 0, | ||
99 | PMU_PG_CMD_ID_ENG_BUF_LOAD, | ||
100 | PMU_PG_CMD_ID_ENG_BUF_UNLOAD, | ||
101 | PMU_PG_CMD_ID_PG_STAT, | ||
102 | PMU_PG_CMD_ID_PG_LOG_INIT, | ||
103 | PMU_PG_CMD_ID_PG_LOG_FLUSH, | ||
104 | PMU_PG_CMD_ID_PG_PARAM, | ||
105 | PMU_PG_CMD_ID_ELPG_INIT, | ||
106 | PMU_PG_CMD_ID_ELPG_POLL_CTXSAVE, | ||
107 | PMU_PG_CMD_ID_ELPG_ABORT_POLL, | ||
108 | PMU_PG_CMD_ID_ELPG_PWR_UP, | ||
109 | PMU_PG_CMD_ID_ELPG_DISALLOW, | ||
110 | PMU_PG_CMD_ID_ELPG_ALLOW, | ||
111 | PMU_PG_CMD_ID_AP, | ||
112 | RM_PMU_PG_CMD_ID_PSI, | ||
113 | RM_PMU_PG_CMD_ID_CG, | ||
114 | PMU_PG_CMD_ID_ZBC_TABLE_UPDATE, | ||
115 | PMU_PG_CMD_ID_PWR_RAIL_GATE_DISABLE = 0x20, | ||
116 | PMU_PG_CMD_ID_PWR_RAIL_GATE_ENABLE, | ||
117 | PMU_PG_CMD_ID_PWR_RAIL_SMU_MSG_DISABLE, | ||
118 | PMU_PMU_PG_CMD_ID_RPPG = 0x24, | ||
119 | }; | ||
120 | |||
121 | enum { | ||
122 | PMU_PG_STAT_CMD_ALLOC_DMEM = 0, | ||
123 | }; | ||
124 | |||
125 | enum { | ||
126 | SLOWDOWN_FACTOR_FPDIV_BY1 = 0, | ||
127 | SLOWDOWN_FACTOR_FPDIV_BY1P5, | ||
128 | SLOWDOWN_FACTOR_FPDIV_BY2, | ||
129 | SLOWDOWN_FACTOR_FPDIV_BY2P5, | ||
130 | SLOWDOWN_FACTOR_FPDIV_BY3, | ||
131 | SLOWDOWN_FACTOR_FPDIV_BY3P5, | ||
132 | SLOWDOWN_FACTOR_FPDIV_BY4, | ||
133 | SLOWDOWN_FACTOR_FPDIV_BY4P5, | ||
134 | SLOWDOWN_FACTOR_FPDIV_BY5, | ||
135 | SLOWDOWN_FACTOR_FPDIV_BY5P5, | ||
136 | SLOWDOWN_FACTOR_FPDIV_BY6, | ||
137 | SLOWDOWN_FACTOR_FPDIV_BY6P5, | ||
138 | SLOWDOWN_FACTOR_FPDIV_BY7, | ||
139 | SLOWDOWN_FACTOR_FPDIV_BY7P5, | ||
140 | SLOWDOWN_FACTOR_FPDIV_BY8, | ||
141 | SLOWDOWN_FACTOR_FPDIV_BY8P5, | ||
142 | SLOWDOWN_FACTOR_FPDIV_BY9, | ||
143 | SLOWDOWN_FACTOR_FPDIV_BY9P5, | ||
144 | SLOWDOWN_FACTOR_FPDIV_BY10, | ||
145 | SLOWDOWN_FACTOR_FPDIV_BY10P5, | ||
146 | SLOWDOWN_FACTOR_FPDIV_BY11, | ||
147 | SLOWDOWN_FACTOR_FPDIV_BY11P5, | ||
148 | SLOWDOWN_FACTOR_FPDIV_BY12, | ||
149 | SLOWDOWN_FACTOR_FPDIV_BY12P5, | ||
150 | SLOWDOWN_FACTOR_FPDIV_BY13, | ||
151 | SLOWDOWN_FACTOR_FPDIV_BY13P5, | ||
152 | SLOWDOWN_FACTOR_FPDIV_BY14, | ||
153 | SLOWDOWN_FACTOR_FPDIV_BY14P5, | ||
154 | SLOWDOWN_FACTOR_FPDIV_BY15, | ||
155 | SLOWDOWN_FACTOR_FPDIV_BY15P5, | ||
156 | SLOWDOWN_FACTOR_FPDIV_BY16, | ||
157 | SLOWDOWN_FACTOR_FPDIV_BY16P5, | ||
158 | SLOWDOWN_FACTOR_FPDIV_BY17 = 0x20, | ||
159 | SLOWDOWN_FACTOR_FPDIV_BY18 = 0x22, | ||
160 | SLOWDOWN_FACTOR_FPDIV_BY19 = 0x24, | ||
161 | SLOWDOWN_FACTOR_FPDIV_BY20 = 0x26, | ||
162 | SLOWDOWN_FACTOR_FPDIV_BY21 = 0x28, | ||
163 | SLOWDOWN_FACTOR_FPDIV_BY22 = 0x2a, | ||
164 | SLOWDOWN_FACTOR_FPDIV_BY23 = 0x2c, | ||
165 | SLOWDOWN_FACTOR_FPDIV_BY24 = 0x2e, | ||
166 | SLOWDOWN_FACTOR_FPDIV_BY25 = 0x30, | ||
167 | SLOWDOWN_FACTOR_FPDIV_BY26 = 0x32, | ||
168 | SLOWDOWN_FACTOR_FPDIV_BY27 = 0x34, | ||
169 | SLOWDOWN_FACTOR_FPDIV_BY28 = 0x36, | ||
170 | SLOWDOWN_FACTOR_FPDIV_BY29 = 0x38, | ||
171 | SLOWDOWN_FACTOR_FPDIV_BY30 = 0x3a, | ||
172 | SLOWDOWN_FACTOR_FPDIV_BY31 = 0x3c, | ||
173 | SLOWDOWN_FACTOR_FPDIV_BYMAX, | ||
174 | }; | ||
175 | |||
176 | #define PMU_PG_PARAM_CMD_GR_INIT_PARAM 0x0U | ||
177 | #define PMU_PG_PARAM_CMD_MS_INIT_PARAM 0x01U | ||
178 | #define PMU_PG_PARAM_CMD_MCLK_CHANGE 0x04U | ||
179 | #define PMU_PG_PARAM_CMD_POST_INIT 0x06U | ||
180 | #define PMU_PG_PARAM_CMD_SUB_FEATURE_MASK_UPDATE 0x07U | ||
181 | |||
182 | #define NVGPU_PMU_GR_FEATURE_MASK_SDIV_SLOWDOWN BIT32(0) | ||
183 | #define NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING BIT32(2) | ||
184 | #define NVGPU_PMU_GR_FEATURE_MASK_RPPG BIT32(3) | ||
185 | #define NVGPU_PMU_GR_FEATURE_MASK_PRIV_RING BIT32(5) | ||
186 | #define NVGPU_PMU_GR_FEATURE_MASK_UNBIND BIT32(6) | ||
187 | #define NVGPU_PMU_GR_FEATURE_MASK_SAVE_GLOBAL_STATE BIT32(7) | ||
188 | #define NVGPU_PMU_GR_FEATURE_MASK_RESET_ENTRY BIT32(8) | ||
189 | #define NVGPU_PMU_GR_FEATURE_MASK_HW_SEQUENCE BIT32(9) | ||
190 | #define NVGPU_PMU_GR_FEATURE_MASK_ELPG_SRAM BIT32(10) | ||
191 | #define NVGPU_PMU_GR_FEATURE_MASK_ELPG_LOGIC BIT32(11) | ||
192 | #define NVGPU_PMU_GR_FEATURE_MASK_ELPG_L2RPPG BIT32(12) | ||
193 | |||
194 | #define NVGPU_PMU_GR_FEATURE_MASK_ALL \ | ||
195 | ( \ | ||
196 | NVGPU_PMU_GR_FEATURE_MASK_SDIV_SLOWDOWN |\ | ||
197 | NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING |\ | ||
198 | NVGPU_PMU_GR_FEATURE_MASK_RPPG |\ | ||
199 | NVGPU_PMU_GR_FEATURE_MASK_PRIV_RING |\ | ||
200 | NVGPU_PMU_GR_FEATURE_MASK_UNBIND |\ | ||
201 | NVGPU_PMU_GR_FEATURE_MASK_SAVE_GLOBAL_STATE |\ | ||
202 | NVGPU_PMU_GR_FEATURE_MASK_RESET_ENTRY |\ | ||
203 | NVGPU_PMU_GR_FEATURE_MASK_HW_SEQUENCE |\ | ||
204 | NVGPU_PMU_GR_FEATURE_MASK_ELPG_SRAM |\ | ||
205 | NVGPU_PMU_GR_FEATURE_MASK_ELPG_LOGIC |\ | ||
206 | NVGPU_PMU_GR_FEATURE_MASK_ELPG_L2RPPG \ | ||
207 | ) | ||
208 | |||
209 | #define NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING BIT32(0) | ||
210 | #define NVGPU_PMU_MS_FEATURE_MASK_SW_ASR BIT32(1) | ||
211 | #define NVGPU_PMU_MS_FEATURE_MASK_RPPG BIT32(8) | ||
212 | #define NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING BIT32(5) | ||
213 | |||
214 | #define NVGPU_PMU_MS_FEATURE_MASK_ALL \ | ||
215 | ( \ | ||
216 | NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING |\ | ||
217 | NVGPU_PMU_MS_FEATURE_MASK_SW_ASR |\ | ||
218 | NVGPU_PMU_MS_FEATURE_MASK_RPPG |\ | ||
219 | NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING \ | ||
220 | ) | ||
221 | |||
222 | |||
223 | struct pmu_pg_cmd_elpg_cmd { | ||
224 | u8 cmd_type; | ||
225 | u8 engine_id; | ||
226 | u16 cmd; | ||
227 | }; | ||
228 | |||
229 | struct pmu_pg_cmd_eng_buf_load_v0 { | ||
230 | u8 cmd_type; | ||
231 | u8 engine_id; | ||
232 | u8 buf_idx; | ||
233 | u8 pad; | ||
234 | u16 buf_size; | ||
235 | u32 dma_base; | ||
236 | u8 dma_offset; | ||
237 | u8 dma_idx; | ||
238 | }; | ||
239 | |||
240 | struct pmu_pg_cmd_eng_buf_load_v1 { | ||
241 | u8 cmd_type; | ||
242 | u8 engine_id; | ||
243 | u8 buf_idx; | ||
244 | u8 pad; | ||
245 | struct flcn_mem_desc { | ||
246 | struct falc_u64 dma_addr; | ||
247 | u16 dma_size; | ||
248 | u8 dma_idx; | ||
249 | } dma_desc; | ||
250 | }; | ||
251 | |||
252 | struct pmu_pg_cmd_eng_buf_load_v2 { | ||
253 | u8 cmd_type; | ||
254 | u8 engine_id; | ||
255 | u8 buf_idx; | ||
256 | u8 pad; | ||
257 | struct flcn_mem_desc_v0 dma_desc; | ||
258 | }; | ||
259 | |||
260 | struct pmu_pg_cmd_gr_init_param { | ||
261 | u8 cmd_type; | ||
262 | u16 sub_cmd_id; | ||
263 | u8 featuremask; | ||
264 | }; | ||
265 | |||
266 | struct pmu_pg_cmd_gr_init_param_v2 { | ||
267 | u8 cmd_type; | ||
268 | u16 sub_cmd_id; | ||
269 | u8 featuremask; | ||
270 | u8 ldiv_slowdown_factor; | ||
271 | }; | ||
272 | |||
273 | struct pmu_pg_cmd_gr_init_param_v1 { | ||
274 | u8 cmd_type; | ||
275 | u16 sub_cmd_id; | ||
276 | u32 featuremask; | ||
277 | }; | ||
278 | |||
279 | struct pmu_pg_cmd_sub_feature_mask_update { | ||
280 | u8 cmd_type; | ||
281 | u16 sub_cmd_id; | ||
282 | u8 ctrl_id; | ||
283 | u32 enabled_mask; | ||
284 | }; | ||
285 | |||
286 | struct pmu_pg_cmd_ms_init_param { | ||
287 | u8 cmd_type; | ||
288 | u16 cmd_id; | ||
289 | u8 psi; | ||
290 | u8 idle_flipped_test_enabled; | ||
291 | u16 psiSettleTimeUs; | ||
292 | u8 rsvd[2]; | ||
293 | u32 support_mask; | ||
294 | u32 abort_timeout_us; | ||
295 | }; | ||
296 | |||
297 | struct pmu_pg_cmd_mclk_change { | ||
298 | u8 cmd_type; | ||
299 | u16 cmd_id; | ||
300 | u8 rsvd; | ||
301 | u32 data; | ||
302 | }; | ||
303 | |||
304 | #define PG_VOLT_RAIL_IDX_MAX 2 | ||
305 | |||
306 | struct pmu_pg_volt_rail { | ||
307 | u8 volt_rail_idx; | ||
308 | u8 sleep_volt_dev_idx; | ||
309 | u8 sleep_vfe_idx; | ||
310 | u32 sleep_voltage_uv; | ||
311 | u32 therm_vid0_cache; | ||
312 | u32 therm_vid1_cache; | ||
313 | }; | ||
314 | |||
315 | struct pmu_pg_cmd_post_init_param { | ||
316 | u8 cmd_type; | ||
317 | u16 cmd_id; | ||
318 | struct pmu_pg_volt_rail pg_volt_rail[PG_VOLT_RAIL_IDX_MAX]; | ||
319 | }; | ||
320 | |||
321 | struct pmu_pg_cmd_stat { | ||
322 | u8 cmd_type; | ||
323 | u8 engine_id; | ||
324 | u16 sub_cmd_id; | ||
325 | u32 data; | ||
326 | }; | ||
327 | |||
328 | struct pmu_pg_cmd { | ||
329 | union { | ||
330 | u8 cmd_type; | ||
331 | struct pmu_pg_cmd_elpg_cmd elpg_cmd; | ||
332 | struct pmu_pg_cmd_eng_buf_load_v0 eng_buf_load_v0; | ||
333 | struct pmu_pg_cmd_eng_buf_load_v1 eng_buf_load_v1; | ||
334 | struct pmu_pg_cmd_eng_buf_load_v2 eng_buf_load_v2; | ||
335 | struct pmu_pg_cmd_stat stat; | ||
336 | struct pmu_pg_cmd_gr_init_param gr_init_param; | ||
337 | struct pmu_pg_cmd_gr_init_param_v1 gr_init_param_v1; | ||
338 | struct pmu_pg_cmd_gr_init_param_v2 gr_init_param_v2; | ||
339 | struct pmu_pg_cmd_ms_init_param ms_init_param; | ||
340 | struct pmu_pg_cmd_mclk_change mclk_change; | ||
341 | struct pmu_pg_cmd_post_init_param post_init; | ||
342 | /* TBD: other pg commands */ | ||
343 | union pmu_ap_cmd ap_cmd; | ||
344 | struct nv_pmu_rppg_cmd rppg_cmd; | ||
345 | struct pmu_pg_cmd_sub_feature_mask_update sf_mask_update; | ||
346 | }; | ||
347 | }; | ||
348 | |||
349 | /* Statistics structure for PG features */ | ||
350 | struct pmu_pg_stats_v2 { | ||
351 | u32 entry_count; | ||
352 | u32 exit_count; | ||
353 | u32 abort_count; | ||
354 | u32 detection_count; | ||
355 | u32 prevention_activate_count; | ||
356 | u32 prevention_deactivate_count; | ||
357 | u32 powered_up_time_us; | ||
358 | u32 entry_latency_us; | ||
359 | u32 exit_latency_us; | ||
360 | u32 resident_time_us; | ||
361 | u32 entry_latency_avg_us; | ||
362 | u32 exit_latency_avg_us; | ||
363 | u32 entry_latency_max_us; | ||
364 | u32 exit_latency_max_us; | ||
365 | u32 total_sleep_time_us; | ||
366 | u32 total_non_sleep_time_us; | ||
367 | }; | ||
368 | |||
369 | struct pmu_pg_stats_v1 { | ||
370 | /* Number of time PMU successfully engaged sleep state */ | ||
371 | u32 entry_count; | ||
372 | /* Number of time PMU exit sleep state */ | ||
373 | u32 exit_count; | ||
374 | /* Number of time PMU aborted in entry sequence */ | ||
375 | u32 abort_count; | ||
376 | /* | ||
377 | * Time for which GPU was neither in Sleep state not | ||
378 | * executing sleep sequence. | ||
379 | */ | ||
380 | u32 poweredup_timeus; | ||
381 | /* Entry and exit latency of current sleep cycle */ | ||
382 | u32 entry_latency_us; | ||
383 | u32 exitlatencyus; | ||
384 | /* Resident time for current sleep cycle. */ | ||
385 | u32 resident_timeus; | ||
386 | /* Rolling average entry and exit latencies */ | ||
387 | u32 entrylatency_avgus; | ||
388 | u32 exitlatency_avgus; | ||
389 | /* Max entry and exit latencies */ | ||
390 | u32 entrylatency_maxus; | ||
391 | u32 exitlatency_maxus; | ||
392 | /* Total time spent in sleep and non-sleep state */ | ||
393 | u32 total_sleep_timeus; | ||
394 | u32 total_nonsleep_timeus; | ||
395 | }; | ||
396 | |||
397 | struct pmu_pg_stats { | ||
398 | u64 pg_entry_start_timestamp; | ||
399 | u64 pg_ingating_start_timestamp; | ||
400 | u64 pg_exit_start_timestamp; | ||
401 | u64 pg_ungating_start_timestamp; | ||
402 | u32 pg_avg_entry_time_us; | ||
403 | u32 pg_ingating_cnt; | ||
404 | u32 pg_ingating_time_us; | ||
405 | u32 pg_avg_exit_time_us; | ||
406 | u32 pg_ungating_count; | ||
407 | u32 pg_ungating_time_us; | ||
408 | u32 pg_gating_cnt; | ||
409 | u32 pg_gating_deny_cnt; | ||
410 | }; | ||
411 | |||
412 | #endif /* NVGPU_PMUIF_GPMUIF_PG_H*/ | ||