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-rw-r--r--include/nvgpu/pmuif/gpmuif_pg.h14
1 files changed, 13 insertions, 1 deletions
diff --git a/include/nvgpu/pmuif/gpmuif_pg.h b/include/nvgpu/pmuif/gpmuif_pg.h
index 69a7ea4..58311ae 100644
--- a/include/nvgpu/pmuif/gpmuif_pg.h
+++ b/include/nvgpu/pmuif/gpmuif_pg.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -33,6 +33,11 @@
33#define PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE (0x00000005U) 33#define PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE (0x00000005U)
34#define PMU_PG_ELPG_ENGINE_MAX PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE 34#define PMU_PG_ELPG_ENGINE_MAX PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE
35 35
36/* Async PG message IDs */
37enum {
38 PMU_PG_MSG_ASYNC_CMD_DISALLOW,
39};
40
36/* PG message */ 41/* PG message */
37enum { 42enum {
38 PMU_PG_ELPG_MSG_INIT_ACK, 43 PMU_PG_ELPG_MSG_INIT_ACK,
@@ -73,12 +78,19 @@ struct pmu_pg_msg_eng_buf_stat {
73 u8 status; 78 u8 status;
74}; 79};
75 80
81struct pmu_pg_msg_async_cmd_resp {
82 u8 msg_type;
83 u8 ctrl_id;
84 u8 msg_id;
85};
86
76struct pmu_pg_msg { 87struct pmu_pg_msg {
77 union { 88 union {
78 u8 msg_type; 89 u8 msg_type;
79 struct pmu_pg_msg_elpg_msg elpg_msg; 90 struct pmu_pg_msg_elpg_msg elpg_msg;
80 struct pmu_pg_msg_stat stat; 91 struct pmu_pg_msg_stat stat;
81 struct pmu_pg_msg_eng_buf_stat eng_buf_stat; 92 struct pmu_pg_msg_eng_buf_stat eng_buf_stat;
93 struct pmu_pg_msg_async_cmd_resp async_cmd_resp;
82 /* TBD: other pg messages */ 94 /* TBD: other pg messages */
83 union pmu_ap_msg ap_msg; 95 union pmu_ap_msg ap_msg;
84 struct nv_pmu_rppg_msg rppg_msg; 96 struct nv_pmu_rppg_msg rppg_msg;