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-rw-r--r--include/nvgpu/pmuif/gpmuif_pg.h424
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diff --git a/include/nvgpu/pmuif/gpmuif_pg.h b/include/nvgpu/pmuif/gpmuif_pg.h
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--- a/include/nvgpu/pmuif/gpmuif_pg.h
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1/*
2 * Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22#ifndef NVGPU_PMUIF_GPMUIF_PG_H
23#define NVGPU_PMUIF_GPMUIF_PG_H
24
25#include "gpmuif_ap.h"
26#include "gpmuif_pg_rppg.h"
27
28/*PG defines*/
29
30/* Identifier for each PG */
31#define PMU_PG_ELPG_ENGINE_ID_GRAPHICS (0x00000000U)
32#define PMU_PG_ELPG_ENGINE_ID_MS (0x00000004U)
33#define PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE (0x00000005U)
34#define PMU_PG_ELPG_ENGINE_MAX PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE
35
36/* Async PG message IDs */
37enum {
38 PMU_PG_MSG_ASYNC_CMD_DISALLOW,
39};
40
41/* PG message */
42enum {
43 PMU_PG_ELPG_MSG_INIT_ACK,
44 PMU_PG_ELPG_MSG_DISALLOW_ACK,
45 PMU_PG_ELPG_MSG_ALLOW_ACK,
46 PMU_PG_ELPG_MSG_FREEZE_ACK,
47 PMU_PG_ELPG_MSG_FREEZE_ABORT,
48 PMU_PG_ELPG_MSG_UNFREEZE_ACK,
49};
50
51struct pmu_pg_msg_elpg_msg {
52 u8 msg_type;
53 u8 engine_id;
54 u16 msg;
55};
56
57enum {
58 PMU_PG_STAT_MSG_RESP_DMEM_OFFSET = 0,
59};
60
61struct pmu_pg_msg_stat {
62 u8 msg_type;
63 u8 engine_id;
64 u16 sub_msg_id;
65 u32 data;
66};
67
68enum {
69 PMU_PG_MSG_ENG_BUF_LOADED,
70 PMU_PG_MSG_ENG_BUF_UNLOADED,
71 PMU_PG_MSG_ENG_BUF_FAILED,
72};
73
74struct pmu_pg_msg_eng_buf_stat {
75 u8 msg_type;
76 u8 engine_id;
77 u8 buf_idx;
78 u8 status;
79};
80
81struct pmu_pg_msg_async_cmd_resp {
82 u8 msg_type;
83 u8 ctrl_id;
84 u8 msg_id;
85};
86
87struct pmu_pg_msg {
88 union {
89 u8 msg_type;
90 struct pmu_pg_msg_elpg_msg elpg_msg;
91 struct pmu_pg_msg_stat stat;
92 struct pmu_pg_msg_eng_buf_stat eng_buf_stat;
93 struct pmu_pg_msg_async_cmd_resp async_cmd_resp;
94 /* TBD: other pg messages */
95 union pmu_ap_msg ap_msg;
96 struct nv_pmu_rppg_msg rppg_msg;
97 };
98};
99
100/* PG commands */
101enum {
102 PMU_PG_ELPG_CMD_INIT,
103 PMU_PG_ELPG_CMD_DISALLOW,
104 PMU_PG_ELPG_CMD_ALLOW,
105 PMU_PG_ELPG_CMD_FREEZE,
106 PMU_PG_ELPG_CMD_UNFREEZE,
107};
108
109enum {
110 PMU_PG_CMD_ID_ELPG_CMD = 0,
111 PMU_PG_CMD_ID_ENG_BUF_LOAD,
112 PMU_PG_CMD_ID_ENG_BUF_UNLOAD,
113 PMU_PG_CMD_ID_PG_STAT,
114 PMU_PG_CMD_ID_PG_LOG_INIT,
115 PMU_PG_CMD_ID_PG_LOG_FLUSH,
116 PMU_PG_CMD_ID_PG_PARAM,
117 PMU_PG_CMD_ID_ELPG_INIT,
118 PMU_PG_CMD_ID_ELPG_POLL_CTXSAVE,
119 PMU_PG_CMD_ID_ELPG_ABORT_POLL,
120 PMU_PG_CMD_ID_ELPG_PWR_UP,
121 PMU_PG_CMD_ID_ELPG_DISALLOW,
122 PMU_PG_CMD_ID_ELPG_ALLOW,
123 PMU_PG_CMD_ID_AP,
124 RM_PMU_PG_CMD_ID_PSI,
125 RM_PMU_PG_CMD_ID_CG,
126 PMU_PG_CMD_ID_ZBC_TABLE_UPDATE,
127 PMU_PG_CMD_ID_PWR_RAIL_GATE_DISABLE = 0x20,
128 PMU_PG_CMD_ID_PWR_RAIL_GATE_ENABLE,
129 PMU_PG_CMD_ID_PWR_RAIL_SMU_MSG_DISABLE,
130 PMU_PMU_PG_CMD_ID_RPPG = 0x24,
131};
132
133enum {
134 PMU_PG_STAT_CMD_ALLOC_DMEM = 0,
135};
136
137enum {
138 SLOWDOWN_FACTOR_FPDIV_BY1 = 0,
139 SLOWDOWN_FACTOR_FPDIV_BY1P5,
140 SLOWDOWN_FACTOR_FPDIV_BY2,
141 SLOWDOWN_FACTOR_FPDIV_BY2P5,
142 SLOWDOWN_FACTOR_FPDIV_BY3,
143 SLOWDOWN_FACTOR_FPDIV_BY3P5,
144 SLOWDOWN_FACTOR_FPDIV_BY4,
145 SLOWDOWN_FACTOR_FPDIV_BY4P5,
146 SLOWDOWN_FACTOR_FPDIV_BY5,
147 SLOWDOWN_FACTOR_FPDIV_BY5P5,
148 SLOWDOWN_FACTOR_FPDIV_BY6,
149 SLOWDOWN_FACTOR_FPDIV_BY6P5,
150 SLOWDOWN_FACTOR_FPDIV_BY7,
151 SLOWDOWN_FACTOR_FPDIV_BY7P5,
152 SLOWDOWN_FACTOR_FPDIV_BY8,
153 SLOWDOWN_FACTOR_FPDIV_BY8P5,
154 SLOWDOWN_FACTOR_FPDIV_BY9,
155 SLOWDOWN_FACTOR_FPDIV_BY9P5,
156 SLOWDOWN_FACTOR_FPDIV_BY10,
157 SLOWDOWN_FACTOR_FPDIV_BY10P5,
158 SLOWDOWN_FACTOR_FPDIV_BY11,
159 SLOWDOWN_FACTOR_FPDIV_BY11P5,
160 SLOWDOWN_FACTOR_FPDIV_BY12,
161 SLOWDOWN_FACTOR_FPDIV_BY12P5,
162 SLOWDOWN_FACTOR_FPDIV_BY13,
163 SLOWDOWN_FACTOR_FPDIV_BY13P5,
164 SLOWDOWN_FACTOR_FPDIV_BY14,
165 SLOWDOWN_FACTOR_FPDIV_BY14P5,
166 SLOWDOWN_FACTOR_FPDIV_BY15,
167 SLOWDOWN_FACTOR_FPDIV_BY15P5,
168 SLOWDOWN_FACTOR_FPDIV_BY16,
169 SLOWDOWN_FACTOR_FPDIV_BY16P5,
170 SLOWDOWN_FACTOR_FPDIV_BY17 = 0x20,
171 SLOWDOWN_FACTOR_FPDIV_BY18 = 0x22,
172 SLOWDOWN_FACTOR_FPDIV_BY19 = 0x24,
173 SLOWDOWN_FACTOR_FPDIV_BY20 = 0x26,
174 SLOWDOWN_FACTOR_FPDIV_BY21 = 0x28,
175 SLOWDOWN_FACTOR_FPDIV_BY22 = 0x2a,
176 SLOWDOWN_FACTOR_FPDIV_BY23 = 0x2c,
177 SLOWDOWN_FACTOR_FPDIV_BY24 = 0x2e,
178 SLOWDOWN_FACTOR_FPDIV_BY25 = 0x30,
179 SLOWDOWN_FACTOR_FPDIV_BY26 = 0x32,
180 SLOWDOWN_FACTOR_FPDIV_BY27 = 0x34,
181 SLOWDOWN_FACTOR_FPDIV_BY28 = 0x36,
182 SLOWDOWN_FACTOR_FPDIV_BY29 = 0x38,
183 SLOWDOWN_FACTOR_FPDIV_BY30 = 0x3a,
184 SLOWDOWN_FACTOR_FPDIV_BY31 = 0x3c,
185 SLOWDOWN_FACTOR_FPDIV_BYMAX,
186};
187
188#define PMU_PG_PARAM_CMD_GR_INIT_PARAM 0x0U
189#define PMU_PG_PARAM_CMD_MS_INIT_PARAM 0x01U
190#define PMU_PG_PARAM_CMD_MCLK_CHANGE 0x04U
191#define PMU_PG_PARAM_CMD_POST_INIT 0x06U
192#define PMU_PG_PARAM_CMD_SUB_FEATURE_MASK_UPDATE 0x07U
193
194#define NVGPU_PMU_GR_FEATURE_MASK_SDIV_SLOWDOWN BIT32(0)
195#define NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING BIT32(2)
196#define NVGPU_PMU_GR_FEATURE_MASK_RPPG BIT32(3)
197#define NVGPU_PMU_GR_FEATURE_MASK_PRIV_RING BIT32(5)
198#define NVGPU_PMU_GR_FEATURE_MASK_UNBIND BIT32(6)
199#define NVGPU_PMU_GR_FEATURE_MASK_SAVE_GLOBAL_STATE BIT32(7)
200#define NVGPU_PMU_GR_FEATURE_MASK_RESET_ENTRY BIT32(8)
201#define NVGPU_PMU_GR_FEATURE_MASK_HW_SEQUENCE BIT32(9)
202#define NVGPU_PMU_GR_FEATURE_MASK_ELPG_SRAM BIT32(10)
203#define NVGPU_PMU_GR_FEATURE_MASK_ELPG_LOGIC BIT32(11)
204#define NVGPU_PMU_GR_FEATURE_MASK_ELPG_L2RPPG BIT32(12)
205
206#define NVGPU_PMU_GR_FEATURE_MASK_ALL \
207 ( \
208 NVGPU_PMU_GR_FEATURE_MASK_SDIV_SLOWDOWN |\
209 NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING |\
210 NVGPU_PMU_GR_FEATURE_MASK_RPPG |\
211 NVGPU_PMU_GR_FEATURE_MASK_PRIV_RING |\
212 NVGPU_PMU_GR_FEATURE_MASK_UNBIND |\
213 NVGPU_PMU_GR_FEATURE_MASK_SAVE_GLOBAL_STATE |\
214 NVGPU_PMU_GR_FEATURE_MASK_RESET_ENTRY |\
215 NVGPU_PMU_GR_FEATURE_MASK_HW_SEQUENCE |\
216 NVGPU_PMU_GR_FEATURE_MASK_ELPG_SRAM |\
217 NVGPU_PMU_GR_FEATURE_MASK_ELPG_LOGIC |\
218 NVGPU_PMU_GR_FEATURE_MASK_ELPG_L2RPPG \