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-rw-r--r--include/nvgpu/pmuif/gpmuif_ap.h256
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diff --git a/include/nvgpu/pmuif/gpmuif_ap.h b/include/nvgpu/pmuif/gpmuif_ap.h
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1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22#ifndef NVGPU_PMUIF_GPMUIF_AP_H
23#define NVGPU_PMUIF_GPMUIF_AP_H
24
25/* PMU Command/Message Interfaces for Adaptive Power */
26/* Macro to get Histogram index */
27#define PMU_AP_HISTOGRAM(idx) (idx)
28#define PMU_AP_HISTOGRAM_CONT (4)
29
30/* Total number of histogram bins */
31#define PMU_AP_CFG_HISTOGRAM_BIN_N (16)
32
33/* Mapping between Idle counters and histograms */
34#define PMU_AP_IDLE_MASK_HIST_IDX_0 (2)
35#define PMU_AP_IDLE_MASK_HIST_IDX_1 (3)
36#define PMU_AP_IDLE_MASK_HIST_IDX_2 (5)
37#define PMU_AP_IDLE_MASK_HIST_IDX_3 (6)
38
39
40/* Mapping between AP_CTRLs and Histograms */
41#define PMU_AP_HISTOGRAM_IDX_GRAPHICS (PMU_AP_HISTOGRAM(1))
42
43/* Mapping between AP_CTRLs and Idle counters */
44#define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1)
45
46/* Adaptive Power Controls (AP_CTRL) */
47enum {
48 PMU_AP_CTRL_ID_GRAPHICS = 0x0,
49 PMU_AP_CTRL_ID_MAX,
50};
51
52/* AP_CTRL Statistics */
53struct pmu_ap_ctrl_stat {
54 /*
55 * Represents whether AP is active or not
56 */
57 u8 b_active;
58
59 /* Idle filter represented by histogram bin index */
60 u8 idle_filter_x;
61 u8 rsvd[2];
62
63 /* Total predicted power saving cycles. */
64 s32 power_saving_h_cycles;
65
66 /* Counts how many times AP gave us -ve power benefits. */
67 u32 bad_decision_count;
68
69 /*
70 * Number of times ap structure needs to skip AP iterations
71 * KICK_CTRL from kernel updates this parameter.
72 */
73 u32 skip_count;
74 u8 bin[PMU_AP_CFG_HISTOGRAM_BIN_N];
75};
76
77/* Parameters initialized by INITn APCTRL command */
78struct pmu_ap_ctrl_init_params {
79 /* Minimum idle filter value in Us */
80 u32 min_idle_filter_us;
81
82 /*
83 * Minimum Targeted Saving in Us. AP will update idle thresholds only
84 * if power saving achieved by updating idle thresholds is greater than
85 * Minimum targeted saving.
86 */
87 u32 min_target_saving_us;
88
89 /* Minimum targeted residency of power feature in Us */
90 u32 power_break_even_us;
91
92 /*
93 * Maximum number of allowed power feature cycles per sample.
94 *
95 * We are allowing at max "pgPerSampleMax" cycles in one iteration of AP
96 * AKA pgPerSampleMax in original algorithm.
97 */
98 u32 cycles_per_sample_max;
99};
100
101/* AP Commands/Message structures */
102
103/*
104 * Structure for Generic AP Commands
105 */
106struct pmu_ap_cmd_common {
107 u8 cmd_type;
108 u16 cmd_id;
109};
110
111/*
112 * Structure for INIT AP command
113 */
114struct pmu_ap_cmd_init {
115 u8 cmd_type;
116 u16 cmd_id;
117 u8 rsvd;
118 u32 pg_sampling_period_us;
119};
120
121/*
122 * Structure for Enable/Disable ApCtrl Commands
123 */
124struct pmu_ap_cmd_enable_ctrl {
125 u8 cmd_type;
126 u16 cmd_id;
127
128 u8 ctrl_id;
129};
130
131struct pmu_ap_cmd_disable_ctrl {
132 u8 cmd_type;
133 u16 cmd_id;
134
135 u8 ctrl_id;
136};
137
138/*
139 * Structure for INIT command
140 */
141struct pmu_ap_cmd_init_ctrl {
142 u8 cmd_type;
143 u16 cmd_id;
144 u8 ctrl_id;
145 struct pmu_ap_ctrl_init_params params;
146};
147
148struct pmu_ap_cmd_init_and_enable_ctrl {
149 u8 cmd_type;
150 u16 cmd_id;
151 u8 ctrl_id;
152 struct pmu_ap_ctrl_init_params params;
153};
154
155/*
156 * Structure for KICK_CTRL command
157 */
158struct pmu_ap_cmd_kick_ctrl {
159 u8 cmd_type;
160 u16 cmd_id;
161 u8 ctrl_id;
162
163 u32 skip_count;
164};
165
166/*
167 * Structure for PARAM command
168 */
169struct pmu_ap_cmd_param {
170 u8 cmd_type;
171 u16 cmd_id;
172 u8 ctrl_id;
173
174 u32 data;
175};
176
177/*
178 * Defines for AP commands
179 */
180enum {
181 PMU_AP_CMD_ID_INIT = 0x0,
182 PMU_AP_CMD_ID_INIT_AND_ENABLE_CTRL,
183 PMU_AP_CMD_ID_ENABLE_CTRL,
184 PMU_AP_CMD_ID_DISABLE_CTRL,
185 PMU_AP_CMD_ID_KICK_CTRL,
186};
187
188/*
189 * AP Command
190 */
191union pmu_ap_cmd {
192 u8 cmd_type;
193 struct pmu_ap_cmd_common cmn;
194 struct pmu_ap_cmd_init init;
195 struct pmu_ap_cmd_init_and_enable_ctrl init_and_enable_ctrl;
196 struct pmu_ap_cmd_enable_ctrl enable_ctrl;
197 struct pmu_ap_cmd_disable_ctrl disable_ctrl;
198 struct pmu_ap_cmd_kick_ctrl kick_ctrl;
199};
200
201/*
202 * Structure for generic AP Message
203 */
204struct pmu_ap_msg_common {
205 u8 msg_type;
206 u16 msg_id;
207};
208
209/*
210 * Structure for INIT_ACK Message
211 */
212struct pmu_ap_msg_init_ack {
213 u8 msg_type;
214 u16 msg_id;
215 u8 ctrl_id;
216 u32 stats_dmem_offset;
217};
218
219/*
220 * Defines for AP messages
221 */
222enum {
223 PMU_AP_MSG_ID_INIT_ACK = 0x0,
224};
225
226/*
227 * AP Message
228 */
229union pmu_ap_msg {
230 u8 msg_type;
231 struct pmu_ap_msg_common cmn;
232 struct pmu_ap_msg_init_ack init_ack;
233};
234
235/*
236 * Adaptive Power Controller
237 */
238struct ap_ctrl {
239 u32 stats_dmem_offset;
240 u32 disable_reason_mask;
241 struct pmu_ap_ctrl_stat stat_cache;
242 u8 b_ready;
243};
244
245/*
246 * Adaptive Power structure
247 *
248 * ap structure provides generic infrastructure to make any power feature
249 * adaptive.
250 */
251struct pmu_ap {
252 u32 supported_mask;
253 struct ap_ctrl ap_ctrl[PMU_AP_CTRL_ID_MAX];
254};
255
256#endif /* NVGPU_PMUIF_GPMUIF_AP_H*/
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-30 18:16:45 -0400