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diff --git a/include/nvgpu/pmu.h b/include/nvgpu/pmu.h
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1/*
2 * Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef NVGPU_PMU_H
24#define NVGPU_PMU_H
25
26#include <nvgpu/kmem.h>
27#include <nvgpu/nvgpu_mem.h>
28#include <nvgpu/allocator.h>
29#include <nvgpu/lock.h>
30#include <nvgpu/cond.h>
31#include <nvgpu/thread.h>
32#include <nvgpu/nvgpu_common.h>
33#include <nvgpu/flcnif_cmn.h>
34#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
35#include <nvgpu/falcon.h>
36
37#define nvgpu_pmu_dbg(g, fmt, args...) \
38 nvgpu_log(g, gpu_dbg_pmu, fmt, ##args)
39
40/* defined by pmu hw spec */
41#define GK20A_PMU_VA_SIZE (512 * 1024 * 1024)
42#define GK20A_PMU_UCODE_SIZE_MAX (256 * 1024)
43#define GK20A_PMU_SEQ_BUF_SIZE 4096
44
45#define GK20A_PMU_TRACE_BUFSIZE 0x4000 /* 4K */
46#define GK20A_PMU_DMEM_BLKSIZE2 8
47
48#define PMU_MODE_MISMATCH_STATUS_MAILBOX_R 6
49#define PMU_MODE_MISMATCH_STATUS_VAL 0xDEADDEAD
50
51/* Falcon Register index */
52#define PMU_FALCON_REG_R0 (0)
53#define PMU_FALCON_REG_R1 (1)
54#define PMU_FALCON_REG_R2 (2)
55#define PMU_FALCON_REG_R3 (3)
56#define PMU_FALCON_REG_R4 (4)
57#define PMU_FALCON_REG_R5 (5)
58#define PMU_FALCON_REG_R6 (6)
59#define PMU_FALCON_REG_R7 (7)
60#define PMU_FALCON_REG_R8 (8)
61#define PMU_FALCON_REG_R9 (9)
62#define PMU_FALCON_REG_R10 (10)
63#define PMU_FALCON_REG_R11 (11)
64#define PMU_FALCON_REG_R12 (12)
65#define PMU_FALCON_REG_R13 (13)
66#define PMU_FALCON_REG_R14 (14)
67#define PMU_FALCON_REG_R15 (15)
68#define PMU_FALCON_REG_IV0 (16)
69#define PMU_FALCON_REG_IV1 (17)
70#define PMU_FALCON_REG_UNDEFINED (18)
71#define PMU_FALCON_REG_EV (19)
72#define PMU_FALCON_REG_SP (20)
73#define PMU_FALCON_REG_PC (21)
74#define PMU_FALCON_REG_IMB (22)
75#define PMU_FALCON_REG_DMB (23)
76#define PMU_FALCON_REG_CSW (24)
77#define PMU_FALCON_REG_CCR (25)
78#define PMU_FALCON_REG_SEC (26)
79#define PMU_FALCON_REG_CTX (27)
80#define PMU_FALCON_REG_EXCI (28)
81#define PMU_FALCON_REG_RSVD0 (29)
82#define PMU_FALCON_REG_RSVD1 (30)
83#define PMU_FALCON_REG_RSVD2 (31)
84#define PMU_FALCON_REG_SIZE (32)
85
86/* Choices for pmu_state */
87#define PMU_STATE_OFF 0U /* PMU is off */
88#define PMU_STATE_STARTING 1U /* PMU is on, but not booted */
89#define PMU_STATE_INIT_RECEIVED 2U /* PMU init message received */
90#define PMU_STATE_ELPG_BOOTING 3U /* PMU is booting */
91#define PMU_STATE_ELPG_BOOTED 4U /* ELPG is initialized */
92#define PMU_STATE_LOADING_PG_BUF 5U /* Loading PG buf */
93#define PMU_STATE_LOADING_ZBC 6U /* Loading ZBC buf */
94#define PMU_STATE_STARTED 7U /* Fully unitialized */
95#define PMU_STATE_EXIT 8U /* Exit PMU state machine */
96
97/* state transition :
98 * OFF => [OFF_ON_PENDING optional] => ON_PENDING => ON => OFF
99 * ON => OFF is always synchronized
100 */
101/* elpg is off */
102#define PMU_ELPG_STAT_OFF 0U
103/* elpg is on */
104#define PMU_ELPG_STAT_ON 1U
105/* elpg is off, ALLOW cmd has been sent, wait for ack */
106#define PMU_ELPG_STAT_ON_PENDING 2U
107/* elpg is on, DISALLOW cmd has been sent, wait for ack */
108#define PMU_ELPG_STAT_OFF_PENDING 3U
109/* elpg is off, caller has requested on, but ALLOW
110 * cmd hasn't been sent due to ENABLE_ALLOW delay
111 */
112#define PMU_ELPG_STAT_OFF_ON_PENDING 4U
113
114#define GK20A_PMU_UCODE_NB_MAX_OVERLAY 32U
115#define GK20A_PMU_UCODE_NB_MAX_DATE_LENGTH 64U
116
117#define PMU_MAX_NUM_SEQUENCES (256U)
118#define PMU_SEQ_BIT_SHIFT (5U)
119#define PMU_SEQ_TBL_SIZE \
120 (PMU_MAX_NUM_SEQUENCES >> PMU_SEQ_BIT_SHIFT)
121
122#define PMU_INVALID_SEQ_DESC (~0)
123
124enum {
125 GK20A_PMU_DMAIDX_UCODE = 0,
126 GK20A_PMU_DMAIDX_VIRT = 1,
127 GK20A_PMU_DMAIDX_PHYS_VID = 2,
128 GK20A_PMU_DMAIDX_PHYS_SYS_COH = 3,
129 GK20A_PMU_DMAIDX_PHYS_SYS_NCOH = 4,
130 GK20A_PMU_DMAIDX_RSVD = 5,
131 GK20A_PMU_DMAIDX_PELPG = 6,
132 GK20A_PMU_DMAIDX_END = 7
133};
134
135enum {
136 PMU_SEQ_STATE_FREE = 0,
137 PMU_SEQ_STATE_PENDING,
138 PMU_SEQ_STATE_USED,
139 PMU_SEQ_STATE_CANCELLED
140};
141
142/*PG defines used by nvpgu-pmu*/
143#define PMU_PG_IDLE_THRESHOLD_SIM 1000
144#define PMU_PG_POST_POWERUP_IDLE_THRESHOLD_SIM 4000000
145/* TBD: QT or else ? */
146#define PMU_PG_IDLE_THRESHOLD 15000
147#define PMU_PG_POST_POWERUP_IDLE_THRESHOLD 1000000
148
149#define PMU_PG_LPWR_FEATURE_RPPG 0x0
150#define PMU_PG_LPWR_FEATURE_MSCG 0x1
151
152#define PMU_MSCG_DISABLED 0U
153#define PMU_MSCG_ENABLED 1U
154
155/* Default Sampling Period of AELPG */
156#define APCTRL_SAMPLING_PERIOD_PG_DEFAULT_US (1000000)
157
158/* Default values of APCTRL parameters */
159#define APCTRL_MINIMUM_IDLE_FILTER_DEFAULT_US (100)
160#define APCTRL_MINIMUM_TARGET_SAVING_DEFAULT_US (10000)
161#define APCTRL_POWER_BREAKEVEN_DEFAULT_US (2000)
162#define APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT (200)
163
164/* pmu load const defines */
165#define PMU_BUSY_CYCLES_NORM_MAX (1000U)
166
167/* RPC */
168#define PMU_RPC_EXECUTE(_stat, _pmu, _unit, _func, _prpc, _size)\
169 do { \
170 memset(&((_prpc)->hdr), 0, sizeof((_prpc)->hdr));\
171 \
172 (_prpc)->hdr.unit_id = PMU_UNIT_##_unit; \
173 (_prpc)->hdr.function = NV_PMU_RPC_ID_##_unit##_##_func;\
174 (_prpc)->hdr.flags = 0x0; \
175 \
176 _stat = nvgpu_pmu_rpc_execute(_pmu, &((_prpc)->hdr), \
177 (sizeof(*(_prpc)) - sizeof((_prpc)->scratch)),\
178 (_size), NULL, NULL, false); \
179 } while (0)
180
181/* RPC blocking call to copy back data from PMU to _prpc */
182#define PMU_RPC_EXECUTE_CPB(_stat, _pmu, _unit, _func, _prpc, _size)\
183 do { \
184 memset(&((_prpc)->hdr), 0, sizeof((_prpc)->hdr));\
185 \
186 (_prpc)->hdr.unit_id = PMU_UNIT_##_unit; \
187 (_prpc)->hdr.function = NV_PMU_RPC_ID_##_unit##_##_func;\
188 (_prpc)->hdr.flags = 0x0; \
189 \
190 _stat = nvgpu_pmu_rpc_execute(_pmu, &((_prpc)->hdr), \
191 (sizeof(*(_prpc)) - sizeof((_prpc)->scratch)),\
192 (_size), NULL, NULL, true); \
193 } while (0)
194
195/* RPC non-blocking with call_back handler option */
196#define PMU_RPC_EXECUTE_CB(_stat, _pmu, _unit, _func, _prpc, _size, _cb, _cbp)\
197 do { \
198 memset(&((_prpc)->hdr), 0, sizeof((_prpc)->hdr));\
199 \
200 (_prpc)->hdr.unit_id = PMU_UNIT_##_unit; \
201 (_prpc)->hdr.function = NV_PMU_RPC_ID_##_unit##_##_func;\
202 (_prpc)->hdr.flags = 0x0; \
203 \
204 _stat = nvgpu_pmu_rpc_execute(_pmu, &((_prpc)->hdr), \
205 (sizeof(*(_prpc)) - sizeof((_prpc)->scratch)),\
206 (_size), _cb, _cbp, false); \
207 } while (0)
208
209typedef void (*pmu_callback)(struct gk20a *, struct pmu_msg *, void *, u32,
210 u32);
211
212struct rpc_handler_payload {
213 void *rpc_buff;
214 bool is_mem_free_set;
215 bool complete;
216};
217
218struct pmu_rpc_desc {
219 void *prpc;
220 u16 size_rpc;
221 u16 size_scratch;
222};
223
224struct pmu_payload {
225 struct {