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1/*
2 * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef NVGPU_PMU_H
24#define NVGPU_PMU_H
25
26#include <nvgpu/kmem.h>
27#include <nvgpu/nvgpu_mem.h>
28#include <nvgpu/allocator.h>
29#include <nvgpu/lock.h>
30#include <nvgpu/cond.h>
31#include <nvgpu/thread.h>
32#include <nvgpu/nvgpu_common.h>
33#include <nvgpu/flcnif_cmn.h>
34#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
35#include <nvgpu/falcon.h>
36
37#define nvgpu_pmu_dbg(g, fmt, args...) \
38 nvgpu_log(g, gpu_dbg_pmu, fmt, ##args)
39
40/* defined by pmu hw spec */
41#define GK20A_PMU_VA_SIZE (512 * 1024 * 1024)
42#define GK20A_PMU_UCODE_SIZE_MAX (256 * 1024)
43#define GK20A_PMU_SEQ_BUF_SIZE 4096
44
45#define GK20A_PMU_TRACE_BUFSIZE 0x4000 /* 4K */
46#define GK20A_PMU_DMEM_BLKSIZE2 8
47
48#define PMU_MODE_MISMATCH_STATUS_MAILBOX_R 6
49#define PMU_MODE_MISMATCH_STATUS_VAL 0xDEADDEAD
50
51/* Falcon Register index */
52#define PMU_FALCON_REG_R0 (0)
53#define PMU_FALCON_REG_R1 (1)
54#define PMU_FALCON_REG_R2 (2)
55#define PMU_FALCON_REG_R3 (3)
56#define PMU_FALCON_REG_R4 (4)
57#define PMU_FALCON_REG_R5 (5)
58#define PMU_FALCON_REG_R6 (6)
59#define PMU_FALCON_REG_R7 (7)
60#define PMU_FALCON_REG_R8 (8)
61#define PMU_FALCON_REG_R9 (9)
62#define PMU_FALCON_REG_R10 (10)
63#define PMU_FALCON_REG_R11 (11)
64#define PMU_FALCON_REG_R12 (12)
65#define PMU_FALCON_REG_R13 (13)
66#define PMU_FALCON_REG_R14 (14)
67#define PMU_FALCON_REG_R15 (15)
68#define PMU_FALCON_REG_IV0 (16)
69#define PMU_FALCON_REG_IV1 (17)
70#define PMU_FALCON_REG_UNDEFINED (18)
71#define PMU_FALCON_REG_EV (19)
72#define PMU_FALCON_REG_SP (20)
73#define PMU_FALCON_REG_PC (21)
74#define PMU_FALCON_REG_IMB (22)
75#define PMU_FALCON_REG_DMB (23)
76#define PMU_FALCON_REG_CSW (24)
77#define PMU_FALCON_REG_CCR (25)
78#define PMU_FALCON_REG_SEC (26)
79#define PMU_FALCON_REG_CTX (27)
80#define PMU_FALCON_REG_EXCI (28)
81#define PMU_FALCON_REG_RSVD0 (29)
82#define PMU_FALCON_REG_RSVD1 (30)
83#define PMU_FALCON_REG_RSVD2 (31)
84#define PMU_FALCON_REG_SIZE (32)
85
86/* Choices for pmu_state */
87#define PMU_STATE_OFF 0U /* PMU is off */
88#define PMU_STATE_STARTING 1U /* PMU is on, but not booted */
89#define PMU_STATE_INIT_RECEIVED 2U /* PMU init message received */
90#define PMU_STATE_ELPG_BOOTING 3U /* PMU is booting */
91#define PMU_STATE_ELPG_BOOTED 4U /* ELPG is initialized */
92#define PMU_STATE_LOADING_PG_BUF 5U /* Loading PG buf */
93#define PMU_STATE_LOADING_ZBC 6U /* Loading ZBC buf */
94#define PMU_STATE_STARTED 7U /* Fully unitialized */
95#define PMU_STATE_EXIT 8U /* Exit PMU state machine */
96
97#define GK20A_PMU_UCODE_NB_MAX_OVERLAY 32U
98#define GK20A_PMU_UCODE_NB_MAX_DATE_LENGTH 64U
99
100#define PMU_MAX_NUM_SEQUENCES (256U)
101#define PMU_SEQ_BIT_SHIFT (5U)
102#define PMU_SEQ_TBL_SIZE \
103 (PMU_MAX_NUM_SEQUENCES >> PMU_SEQ_BIT_SHIFT)
104
105#define PMU_INVALID_SEQ_DESC (~0)
106
107enum {
108 GK20A_PMU_DMAIDX_UCODE = 0,
109 GK20A_PMU_DMAIDX_VIRT = 1,
110 GK20A_PMU_DMAIDX_PHYS_VID = 2,
111 GK20A_PMU_DMAIDX_PHYS_SYS_COH = 3,
112 GK20A_PMU_DMAIDX_PHYS_SYS_NCOH = 4,
113 GK20A_PMU_DMAIDX_RSVD = 5,
114 GK20A_PMU_DMAIDX_PELPG = 6,
115 GK20A_PMU_DMAIDX_END = 7
116};
117
118enum {
119 PMU_SEQ_STATE_FREE = 0,
120 PMU_SEQ_STATE_PENDING,
121 PMU_SEQ_STATE_USED,
122 PMU_SEQ_STATE_CANCELLED
123};
124
125/*PG defines used by nvpgu-pmu*/
126#define PMU_PG_IDLE_THRESHOLD_SIM 1000
127#define PMU_PG_POST_POWERUP_IDLE_THRESHOLD_SIM 4000000
128/* TBD: QT or else ? */
129#define PMU_PG_IDLE_THRESHOLD 15000
130#define PMU_PG_POST_POWERUP_IDLE_THRESHOLD 1000000
131
132#define PMU_PG_LPWR_FEATURE_RPPG 0x0
133#define PMU_PG_LPWR_FEATURE_MSCG 0x1
134
135#define PMU_MSCG_DISABLED 0U
136#define PMU_MSCG_ENABLED 1U
137
138/* Default Sampling Period of AELPG */
139#define APCTRL_SAMPLING_PERIOD_PG_DEFAULT_US (1000000)
140
141/* Default values of APCTRL parameters */
142#define APCTRL_MINIMUM_IDLE_FILTER_DEFAULT_US (100)
143#define APCTRL_MINIMUM_TARGET_SAVING_DEFAULT_US (10000)
144#define APCTRL_POWER_BREAKEVEN_DEFAULT_US (2000)
145#define APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT (200)
146
147/* pmu load const defines */
148#define PMU_BUSY_CYCLES_NORM_MAX (1000U)
149
150/* RPC */
151#define PMU_RPC_EXECUTE(_stat, _pmu, _unit, _func, _prpc, _size)\
152 do { \
153 memset(&((_prpc)->hdr), 0, sizeof((_prpc)->hdr));\
154 \
155 (_prpc)->hdr.unit_id = PMU_UNIT_##_unit; \
156 (_prpc)->hdr.function = NV_PMU_RPC_ID_##_unit##_##_func;\
157 (_prpc)->hdr.flags = 0x0; \
158 \
159 _stat = nvgpu_pmu_rpc_execute(_pmu, &((_prpc)->hdr), \
160 (sizeof(*(_prpc)) - sizeof((_prpc)->scratch)),\
161 (_size), NULL, NULL, false); \
162 } while (0)
163
164/* RPC blocking call to copy back data from PMU to _prpc */
165#define PMU_RPC_EXECUTE_CPB(_stat, _pmu, _unit, _func, _prpc, _size)\
166 do { \
167 memset(&((_prpc)->hdr), 0, sizeof((_prpc)->hdr));\
168 \
169 (_prpc)->hdr.unit_id = PMU_UNIT_##_unit; \
170 (_prpc)->hdr.function = NV_PMU_RPC_ID_##_unit##_##_func;\
171 (_prpc)->hdr.flags = 0x0; \
172 \
173 _stat = nvgpu_pmu_rpc_execute(_pmu, &((_prpc)->hdr), \
174 (sizeof(*(_prpc)) - sizeof((_prpc)->scratch)),\
175 (_size), NULL, NULL, true); \
176 } while (0)
177
178/* RPC non-blocking with call_back handler option */
179#define PMU_RPC_EXECUTE_CB(_stat, _pmu, _unit, _func, _prpc, _size, _cb, _cbp)\
180 do { \
181 memset(&((_prpc)->hdr), 0, sizeof((_prpc)->hdr));\
182 \
183 (_prpc)->hdr.unit_id = PMU_UNIT_##_unit; \
184 (_prpc)->hdr.function = NV_PMU_RPC_ID_##_unit##_##_func;\
185 (_prpc)->hdr.flags = 0x0; \
186 \
187 _stat = nvgpu_pmu_rpc_execute(_pmu, &((_prpc)->hdr), \
188 (sizeof(*(_prpc)) - sizeof((_prpc)->scratch)),\
189 (_size), _cb, _cbp, false); \
190 } while (0)
191
192typedef void (*pmu_callback)(struct gk20a *, struct pmu_msg *, void *, u32,
193 u32);
194
195struct rpc_handler_payload {
196 void *rpc_buff;
197 bool is_mem_free_set;
198 bool complete;
199};
200
201struct pmu_rpc_desc {
202 void *prpc;
203 u16 size_rpc;
204 u16 size_scratch;
205};
206
207struct pmu_payload {
208 struct {
209 void *buf;
210 u32 offset;
211 u32 size;
212 u32 fb_size;
213 } in, out;
214 struct pmu_rpc_desc rpc;
215};
216
217struct pmu_ucode_desc {
218 u32 descriptor_size;
219 u32 image_size;
220 u32 tools_version;
221 u32 app_version;
222 char date[GK20A_PMU_UCODE_NB_MAX_DATE_LENGTH];
223 u32 bootloader_start_offset;
224 u32 bootloader_size;
225 u32 bootloader_imem_offset;
226 u32 bootloader_ent