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diff --git a/include/nvgpu/mm.h b/include/nvgpu/mm.h
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1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef NVGPU_MM_H
24#define NVGPU_MM_H
25
26#include <nvgpu/types.h>
27#include <nvgpu/cond.h>
28#include <nvgpu/thread.h>
29#include <nvgpu/lock.h>
30#include <nvgpu/atomic.h>
31#include <nvgpu/nvgpu_mem.h>
32#include <nvgpu/allocator.h>
33#include <nvgpu/list.h>
34#include <nvgpu/sizes.h>
35
36struct gk20a;
37struct vm_gk20a;
38struct nvgpu_mem;
39struct nvgpu_pd_cache;
40
41#define NVGPU_MM_MMU_FAULT_TYPE_OTHER_AND_NONREPLAY 0
42#define NVGPU_MM_MMU_FAULT_TYPE_REPLAY 1
43
44#define FAULT_TYPE_NUM 2 /* replay and nonreplay faults */
45
46struct mmu_fault_info {
47 u64 inst_ptr;
48 u32 inst_aperture;
49 u64 fault_addr;
50 u32 fault_addr_aperture;
51 u32 timestamp_lo;
52 u32 timestamp_hi;
53 u32 mmu_engine_id;
54 u32 gpc_id;
55 u32 client_type;
56 u32 client_id;
57 u32 fault_type;
58 u32 access_type;
59 u32 protected_mode;
60 u32 replayable_fault;
61 u32 replay_fault_en;
62 u32 valid;
63 u32 faulted_pbdma;
64 u32 faulted_engine;
65 u32 faulted_subid;
66 u32 chid;
67 struct channel_gk20a *refch;
68 const char *client_type_desc;
69 const char *fault_type_desc;
70 const char *client_id_desc;
71};
72
73enum nvgpu_flush_op {
74 NVGPU_FLUSH_DEFAULT,
75 NVGPU_FLUSH_FB,
76 NVGPU_FLUSH_L2_INV,
77 NVGPU_FLUSH_L2_FLUSH,
78 NVGPU_FLUSH_CBC_CLEAN,
79};
80
81struct mm_gk20a {
82 struct gk20a *g;
83
84 /* GPU VA default sizes address spaces for channels */
85 struct {
86 u64 user_size; /* userspace-visible GPU VA region */
87 u64 kernel_size; /* kernel-only GPU VA region */
88 } channel;
89
90 struct {
91 u32 aperture_size;
92 struct vm_gk20a *vm;
93 struct nvgpu_mem inst_block;
94 } bar1;
95
96 struct {
97 u32 aperture_size;
98 struct vm_gk20a *vm;
99 struct nvgpu_mem inst_block;
100 } bar2;
101
102 struct {
103 u32 aperture_size;
104 struct vm_gk20a *vm;
105 struct nvgpu_mem inst_block;
106 } pmu;
107
108 struct {
109 /* using pmu vm currently */
110 struct nvgpu_mem inst_block;
111 } hwpm;
112
113 struct {
114 struct vm_gk20a *vm;
115 struct nvgpu_mem inst_block;
116 } perfbuf;
117
118 struct {
119 struct vm_gk20a *vm;
120 } cde;
121
122 struct {
123 struct vm_gk20a *vm;
124 } ce;
125
126 struct nvgpu_pd_cache *pd_cache;
127
128 struct nvgpu_mutex l2_op_lock;
129 struct nvgpu_mutex tlb_lock;
130 struct nvgpu_mutex priv_lock;
131
132 struct nvgpu_mem bar2_desc;
133
134 struct nvgpu_mem hw_fault_buf[FAULT_TYPE_NUM];
135 struct mmu_fault_info fault_info[FAULT_TYPE_NUM];
136 struct nvgpu_mutex hub_isr_mutex;
137
138 /*
139 * Separate function to cleanup the CE since it requires a channel to
140 * be closed which must happen before fifo cleanup.
141 */
142 void (*remove_ce_support)(struct mm_gk20a *mm);
143 void (*remove_support)(struct mm_gk20a *mm);
144 bool sw_ready;
145 int physical_bits;
146 bool use_full_comp_tag_line;
147 bool ltc_enabled_current;
148 bool ltc_enabled_target;
149 bool disable_bigpage;
150
151 struct nvgpu_mem sysmem_flush;
152
153 u32 pramin_window;
154 struct nvgpu_spinlock pramin_window_lock;
155
156 struct {
157 size_t size;
158 u64 base;
159 size_t bootstrap_size;
160 u64 bootstrap_base;
161
162 struct nvgpu_allocator allocator;
163 struct nvgpu_allocator bootstrap_allocator;
164
165 u32 ce_ctx_id;
166 volatile bool cleared;
167 struct nvgpu_mutex first_clear_mutex;
168
169 struct nvgpu_list_node clear_list_head;
170 struct nvgpu_mutex clear_list_mutex;
171
172 struct nvgpu_cond clearing_thread_cond;
173 struct nvgpu_thread clearing_thread;
174 struct nvgpu_mutex clearing_thread_lock;
175 nvgpu_atomic_t pause_count;
176
177 nvgpu_atomic64_t bytes_pending;
178 } vidmem;
179
180 struct nvgpu_mem mmu_wr_mem;
181 struct nvgpu_mem mmu_rd_mem;
182};
183
184#define gk20a_from_mm(mm) ((mm)->g)
185#define gk20a_from_vm(vm) ((vm)->mm->g)
186
187static inline int bar1_aperture_size_mb_gk20a(void)
188{
189 return 16; /* 16MB is more than enough atm. */
190}
191
192/* The maximum GPU VA range supported */
193#define NV_GMMU_VA_RANGE 38
194
195/* The default userspace-visible GPU VA size */
196#define NV_MM_DEFAULT_USER_SIZE (1ULL << 37)
197
198/* The default kernel-reserved GPU VA size */
199#define NV_MM_DEFAULT_KERNEL_SIZE (1ULL << 32)
200
201/*
202 * When not using unified address spaces, the bottom 56GB of the space are used
203 * for small pages, and the remaining high memory is used for large pages.
204 */
205static inline u64 nvgpu_gmmu_va_small_page_limit(void)
206{
207 return ((u64)SZ_1G * 56U);
208}
209
210u32 nvgpu_vm_get_pte_size(struct vm_gk20a *vm, u64 base, u64 size);
211
212void nvgpu_init_mm_ce_context(struct gk20a *g);
213int nvgpu_init_mm_support(struct gk20a *g);
214int nvgpu_init_mm_setup_hw(struct gk20a *g);
215
216u64 nvgpu_inst_block_addr(struct gk20a *g, struct nvgpu_mem *mem);
217void nvgpu_free_inst_block(struct gk20a *g, struct nvgpu_mem *inst_block);
218
219int nvgpu_mm_suspend(struct gk20a *g);
220u32 nvgpu_mm_get_default_big_page_size(struct gk20a *g);
221u32 nvgpu_mm_get_available_big_page_sizes(struct gk20a *g);
222
223#endif /* NVGPU_MM_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-30 12:16:21 -0400