diff options
Diffstat (limited to 'include/nvgpu/hw_sim_pci.h')
| -rw-r--r-- | include/nvgpu/hw_sim_pci.h | 2169 |
1 files changed, 2169 insertions, 0 deletions
diff --git a/include/nvgpu/hw_sim_pci.h b/include/nvgpu/hw_sim_pci.h new file mode 100644 index 0000000..32dbeb4 --- /dev/null +++ b/include/nvgpu/hw_sim_pci.h | |||
| @@ -0,0 +1,2169 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2012-2018, NVIDIA Corporation. | ||
| 3 | * | ||
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
| 5 | * copy of this software and associated documentation files (the "Software"), | ||
| 6 | * to deal in the Software without restriction, including without limitation | ||
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
| 8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
| 9 | * Software is furnished to do so, subject to the following conditions: | ||
| 10 | * | ||
| 11 | * The above copyright notice and this permission notice shall be included in | ||
| 12 | * all copies or substantial portions of the Software. | ||
| 13 | * | ||
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
| 17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
| 18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
| 19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
| 20 | * DEALINGS IN THE SOFTWARE. | ||
| 21 | */ | ||
| 22 | |||
| 23 | /* | ||
| 24 | * Function naming determines intended use: | ||
| 25 | * | ||
| 26 | * <x>_r(void) : Returns the offset for register <x>. | ||
| 27 | * | ||
| 28 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
| 29 | * | ||
| 30 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
| 31 | * | ||
| 32 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
| 33 | * and masked to place it at field <y> of register <x>. This value | ||
| 34 | * can be |'d with others to produce a full register value for | ||
| 35 | * register <x>. | ||
| 36 | * | ||
| 37 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
| 38 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
| 39 | * register <x>. | ||
| 40 | * | ||
| 41 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
| 42 | * to place it at field <y> of register <x>. This value can be |'d | ||
| 43 | * with others to produce a full register value for <x>. | ||
| 44 | * | ||
| 45 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
| 46 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
| 47 | * This value is suitable for direct comparison with other unshifted | ||
| 48 | * values appropriate for use in field <y> of register <x>. | ||
| 49 | * | ||
| 50 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
| 51 | * field <y> of register <x>. This value is suitable for direct | ||
| 52 | * comparison with unshifted values appropriate for use in field <y> | ||
| 53 | * of register <x>. | ||
| 54 | */ | ||
| 55 | |||
| 56 | #ifndef __hw_sim_pci_h__ | ||
| 57 | #define __hw_sim_pci_h__ | ||
| 58 | /*This file is autogenerated. Do not edit. */ | ||
| 59 | |||
| 60 | static inline u32 sim_r(void) | ||
| 61 | { | ||
| 62 | return 0x0008f000U; | ||
| 63 | } | ||
| 64 | static inline u32 sim_send_ring_r(void) | ||
| 65 | { | ||
| 66 | return 0x00000000U; | ||
| 67 | } | ||
| 68 | static inline u32 sim_send_ring_target_s(void) | ||
| 69 | { | ||
| 70 | return 2U; | ||
| 71 | } | ||
| 72 | static inline u32 sim_send_ring_target_f(u32 v) | ||
| 73 | { | ||
| 74 | return (v & 0x3U) << 0U; | ||
| 75 | } | ||
| 76 | static inline u32 sim_send_ring_target_m(void) | ||
| 77 | { | ||
| 78 | return 0x3U << 0U; | ||
| 79 | } | ||
| 80 | static inline u32 sim_send_ring_target_v(u32 r) | ||
| 81 | { | ||
| 82 | return (r >> 0U) & 0x3U; | ||
| 83 | } | ||
| 84 | static inline u32 sim_send_ring_target_phys_init_v(void) | ||
| 85 | { | ||
| 86 | return 0x00000001U; | ||
| 87 | } | ||
| 88 | static inline u32 sim_send_ring_target_phys_init_f(void) | ||
| 89 | { | ||
| 90 | return 0x1U; | ||
| 91 | } | ||
| 92 | static inline u32 sim_send_ring_target_phys__init_v(void) | ||
| 93 | { | ||
| 94 | return 0x00000001U; | ||
| 95 | } | ||
| 96 | static inline u32 sim_send_ring_target_phys__init_f(void) | ||
| 97 | { | ||
| 98 | return 0x1U; | ||
| 99 | } | ||
| 100 | static inline u32 sim_send_ring_target_phys__prod_v(void) | ||
| 101 | { | ||
| 102 | return 0x00000001U; | ||
| 103 | } | ||
| 104 | static inline u32 sim_send_ring_target_phys__prod_f(void) | ||
| 105 | { | ||
| 106 | return 0x1U; | ||
| 107 | } | ||
| 108 | static inline u32 sim_send_ring_target_phys_nvm_v(void) | ||
| 109 | { | ||
| 110 | return 0x00000001U; | ||
| 111 | } | ||
| 112 | static inline u32 sim_send_ring_target_phys_nvm_f(void) | ||
| 113 | { | ||
| 114 | return 0x1U; | ||
| 115 | } | ||
| 116 | static inline u32 sim_send_ring_target_phys_pci_v(void) | ||
| 117 | { | ||
| 118 | return 0x00000002U; | ||
| 119 | } | ||
| 120 | static inline u32 sim_send_ring_target_phys_pci_f(void) | ||
| 121 | { | ||
| 122 | return 0x2U; | ||
| 123 | } | ||
| 124 | static inline u32 sim_send_ring_target_phys_pci_coherent_v(void) | ||
| 125 | { | ||
| 126 | return 0x00000003U; | ||
| 127 | } | ||
| 128 | static inline u32 sim_send_ring_target_phys_pci_coherent_f(void) | ||
| 129 | { | ||
| 130 | return 0x3U; | ||
| 131 | } | ||
| 132 | static inline u32 sim_send_ring_status_s(void) | ||
| 133 | { | ||
| 134 | return 1U; | ||
| 135 | } | ||
| 136 | static inline u32 sim_send_ring_status_f(u32 v) | ||
| 137 | { | ||
| 138 | return (v & 0x1U) << 3U; | ||
| 139 | } | ||
| 140 | static inline u32 sim_send_ring_status_m(void) | ||
| 141 | { | ||
| 142 | return 0x1U << 3U; | ||
| 143 | } | ||
| 144 | static inline u32 sim_send_ring_status_v(u32 r) | ||
| 145 | { | ||
| 146 | return (r >> 3U) & 0x1U; | ||
| 147 | } | ||
| 148 | static inline u32 sim_send_ring_status_init_v(void) | ||
| 149 | { | ||
| 150 | return 0x00000000U; | ||
| 151 | } | ||
| 152 | static inline u32 sim_send_ring_status_init_f(void) | ||
| 153 | { | ||
| 154 | return 0x0U; | ||
| 155 | } | ||
| 156 | static inline u32 sim_send_ring_status__init_v(void) | ||
| 157 | { | ||
| 158 | return 0x00000000U; | ||
| 159 | } | ||
| 160 | static inline u32 sim_send_ring_status__init_f(void) | ||
| 161 | { | ||
| 162 | return 0x0U; | ||
| 163 | } | ||
| 164 | static inline u32 sim_send_ring_status__prod_v(void) | ||
| 165 | { | ||
| 166 | return 0x00000000U; | ||
| 167 | } | ||
| 168 | static inline u32 sim_send_ring_status__prod_f(void) | ||
| 169 | { | ||
| 170 | return 0x0U; | ||
| 171 | } | ||
| 172 | static inline u32 sim_send_ring_status_invalid_v(void) | ||
| 173 | { | ||
| 174 | return 0x00000000U; | ||
| 175 | } | ||
| 176 | static inline u32 sim_send_ring_status_invalid_f(void) | ||
| 177 | { | ||
| 178 | return 0x0U; | ||
| 179 | } | ||
| 180 | static inline u32 sim_send_ring_status_valid_v(void) | ||
| 181 | { | ||
| 182 | return 0x00000001U; | ||
| 183 | } | ||
| 184 | static inline u32 sim_send_ring_status_valid_f(void) | ||
| 185 | { | ||
| 186 | return 0x8U; | ||
| 187 | } | ||
| 188 | static inline u32 sim_send_ring_size_s(void) | ||
| 189 | { | ||
| 190 | return 2U; | ||
| 191 | } | ||
| 192 | static inline u32 sim_send_ring_size_f(u32 v) | ||
| 193 | { | ||
| 194 | return (v & 0x3U) << 4U; | ||
| 195 | } | ||
| 196 | static inline u32 sim_send_ring_size_m(void) | ||
| 197 | { | ||
| 198 | return 0x3U << 4U; | ||
| 199 | } | ||
| 200 | static inline u32 sim_send_ring_size_v(u32 r) | ||
| 201 | { | ||
| 202 | return (r >> 4U) & 0x3U; | ||
| 203 | } | ||
| 204 | static inline u32 sim_send_ring_size_init_v(void) | ||
| 205 | { | ||
| 206 | return 0x00000000U; | ||
| 207 | } | ||
| 208 | static inline u32 sim_send_ring_size_init_f(void) | ||
| 209 | { | ||
| 210 | return 0x0U; | ||
| 211 | } | ||
| 212 | static inline u32 sim_send_ring_size__init_v(void) | ||
| 213 | { | ||
| 214 | return 0x00000000U; | ||
| 215 | } | ||
| 216 | static inline u32 sim_send_ring_size__init_f(void) | ||
| 217 | { | ||
| 218 | return 0x0U; | ||
| 219 | } | ||
| 220 | static inline u32 sim_send_ring_size__prod_v(void) | ||
| 221 | { | ||
| 222 | return 0x00000000U; | ||
| 223 | } | ||
| 224 | static inline u32 sim_send_ring_size__prod_f(void) | ||
| 225 | { | ||
| 226 | return 0x0U; | ||
| 227 | } | ||
| 228 | static inline u32 sim_send_ring_size_4kb_v(void) | ||
| 229 | { | ||
