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-rw-r--r--include/nvgpu/hw_sim_pci.h2169
1 files changed, 0 insertions, 2169 deletions
diff --git a/include/nvgpu/hw_sim_pci.h b/include/nvgpu/hw_sim_pci.h
deleted file mode 100644
index 32dbeb4..0000000
--- a/include/nvgpu/hw_sim_pci.h
+++ /dev/null
@@ -1,2169 +0,0 @@
1/*
2 * Copyright (c) 2012-2018, NVIDIA Corporation.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23 /*
24 * Function naming determines intended use:
25 *
26 * <x>_r(void) : Returns the offset for register <x>.
27 *
28 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
29 *
30 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
31 *
32 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
33 * and masked to place it at field <y> of register <x>. This value
34 * can be |'d with others to produce a full register value for
35 * register <x>.
36 *
37 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
38 * value can be ~'d and then &'d to clear the value of field <y> for
39 * register <x>.
40 *
41 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
42 * to place it at field <y> of register <x>. This value can be |'d
43 * with others to produce a full register value for <x>.
44 *
45 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
46 * <x> value 'r' after being shifted to place its LSB at bit 0.
47 * This value is suitable for direct comparison with other unshifted
48 * values appropriate for use in field <y> of register <x>.
49 *
50 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
51 * field <y> of register <x>. This value is suitable for direct
52 * comparison with unshifted values appropriate for use in field <y>
53 * of register <x>.
54 */
55
56#ifndef __hw_sim_pci_h__
57#define __hw_sim_pci_h__
58/*This file is autogenerated. Do not edit. */
59
60static inline u32 sim_r(void)
61{
62 return 0x0008f000U;
63}
64static inline u32 sim_send_ring_r(void)
65{
66 return 0x00000000U;
67}
68static inline u32 sim_send_ring_target_s(void)
69{
70 return 2U;
71}
72static inline u32 sim_send_ring_target_f(u32 v)
73{
74 return (v & 0x3U) << 0U;
75}
76static inline u32 sim_send_ring_target_m(void)
77{
78 return 0x3U << 0U;
79}
80static inline u32 sim_send_ring_target_v(u32 r)
81{
82 return (r >> 0U) & 0x3U;
83}
84static inline u32 sim_send_ring_target_phys_init_v(void)
85{
86 return 0x00000001U;
87}
88static inline u32 sim_send_ring_target_phys_init_f(void)
89{
90 return 0x1U;
91}
92static inline u32 sim_send_ring_target_phys__init_v(void)
93{
94 return 0x00000001U;
95}
96static inline u32 sim_send_ring_target_phys__init_f(void)
97{
98 return 0x1U;
99}
100static inline u32 sim_send_ring_target_phys__prod_v(void)
101{
102 return 0x00000001U;
103}
104static inline u32 sim_send_ring_target_phys__prod_f(void)
105{
106 return 0x1U;
107}
108static inline u32 sim_send_ring_target_phys_nvm_v(void)
109{
110 return 0x00000001U;
111}
112static inline u32 sim_send_ring_target_phys_nvm_f(void)
113{
114 return 0x1U;
115}
116static inline u32 sim_send_ring_target_phys_pci_v(void)
117{
118 return 0x00000002U;
119}
120static inline u32 sim_send_ring_target_phys_pci_f(void)
121{
122 return 0x2U;
123}
124static inline u32 sim_send_ring_target_phys_pci_coherent_v(void)
125{
126 return 0x00000003U;
127}
128static inline u32 sim_send_ring_target_phys_pci_coherent_f(void)
129{
130 return 0x3U;
131}
132static inline u32 sim_send_ring_status_s(void)
133{
134 return 1U;
135}
136static inline u32 sim_send_ring_status_f(u32 v)
137{
138 return (v & 0x1U) << 3U;
139}
140static inline u32 sim_send_ring_status_m(void)
141{
142 return 0x1U << 3U;
143}
144static inline u32 sim_send_ring_status_v(u32 r)
145{
146 return (r >> 3U) & 0x1U;
147}
148static inline u32 sim_send_ring_status_init_v(void)
149{
150 return 0x00000000U;
151}
152static inline u32 sim_send_ring_status_init_f(void)
153{
154 return 0x0U;
155}
156static inline u32 sim_send_ring_status__init_v(void)
157{
158 return 0x00000000U;
159}
160static inline u32 sim_send_ring_status__init_f(void)
161{
162 return 0x0U;
163}
164static inline u32 sim_send_ring_status__prod_v(void)
165{
166 return 0x00000000U;
167}
168static inline u32 sim_send_ring_status__prod_f(void)
169{
170 return 0x0U;
171}
172static inline u32 sim_send_ring_status_invalid_v(void)
173{
174 return 0x00000000U;
175}
176static inline u32 sim_send_ring_status_invalid_f(void)
177{
178 return 0x0U;
179}
180static inline u32 sim_send_ring_status_valid_v(void)
181{
182 return 0x00000001U;
183}
184static inline u32 sim_send_ring_status_valid_f(void)
185{
186 return 0x8U;
187}
188static inline u32 sim_send_ring_size_s(void)
189{
190 return 2U;
191}
192static inline u32 sim_send_ring_size_f(u32 v)
193{
194 return (v & 0x3U) << 4U;
195}
196static inline u32 sim_send_ring_size_m(void)
197{
198 return 0x3U << 4U;
199}
200static inline u32 sim_send_ring_size_v(u32 r)
201{
202 return (r >> 4U) & 0x3U;
203}
204static inline u32 sim_send_ring_size_init_v(void)
205{
206 return 0x00000000U;
207}
208static inline u32 sim_send_ring_size_init_f(void)
209{
210 return 0x0U;
211}
212static inline u32 sim_send_ring_size__init_v(void)
213{
214 return 0x00000000U;
215}
216static inline u32 sim_send_ring_size__init_f(void)
217{
218 return 0x0U;
219}
220static inline u32 sim_send_ring_size__prod_v(void)
221{
222 return 0x00000000U;
223}
224static inline u32 sim_send_ring_size__prod_f(void)
225{
226 return 0x0U;
227}
228static inline u32 sim_send_ring_size_4kb_v(void)
229{
230 return 0x00000000U;
231}
232static inline u32 sim_send_ring_size_4kb_f(void)
233{
234 return 0x0U;
235}
236static inline u32 sim_send_ring_size_8kb_v(void)
237{
238 return 0x00000001U;
239}
240static inline u32 sim_send_ring_size_8kb_f(void)
241{
242 return 0x10U;
243}
244static inline u32 sim_send_ring_size_12kb_v(void)
245{
246 return 0x00000002U;
247}
248static inline u32 sim_send_ring_size_12kb_f(void)
249{
250 return 0x20U;
251}
252static inline u32 sim_send_ring_size_16kb_v(void)
253{
254 return 0x00000003U;
255}
256static inline u32 sim_send_ring_size_16kb_f(void)
257{
258 return 0x30U;
259}
260static inline u32 sim_send_ring_gp_in_ring_s(void)
261{
262 return 1U;
263}
264static inline u32 sim_send_ring_gp_in_ring_f(u32 v)
265{
266 return (v & 0x1) << 11U;
267}
268static inline u32 sim_send_ring_gp_in_ring_m(void)
269{
270 return 0x1 << 11U;
271}
272static inline u32 sim_send_ring_gp_in_ring_v(u32 r)
273{
274 return (r >> 11) & 0x1U;
275}
276static inline u32 sim_send_ring_gp_in_ring__init_v(void)
277{
278 return 0x00000000U;
279}
280static inline u32 sim_send_ring_gp_in_ring__init_f(void)
281{
282 return 0x0U;
283}
284static inline u32 sim_send_ring_gp_in_ring__prod_v(void)
285{
286 return 0x00000000U;
287}
288static inline u32 sim_send_ring_gp_in_ring__prod_f(void)
289{
290 return 0x0U;
291}
292static inline u32 sim_send_ring_gp_in_ring_no_v(void)
293{
294 return 0x00000000U;
295}
296static inline u32 sim_send_ring_gp_in_ring_no_f(void)
297{
298 return 0x0U;
299}
300static inline u32 sim_send_ring_gp_in_ring_yes_v(void)
301{
302 return 0x00000001U;
303}
304static inline u32 sim_send_ring_gp_in_ring_yes_f(void)
305{
306 return 0x800U;
307}
308static inline u32 sim_send_ring_addr_lo_s(void)
309{
310 return 20U;
311}
312static inline u32 sim_send_ring_addr_lo_f(u32 v)
313{
314 return (v & 0xfffffU) << 12U;
315}
316static inline u32 sim_send_ring_addr_lo_m(void)
317{
318 return 0xfffffU << 12U;
319}
320static inline u32 sim_send_ring_addr_lo_v(u32 r)
321{
322 return (r >> 12U) & 0xfffffU;
323}
324static inline u32 sim_send_ring_addr_lo__init_v(void)
325{
326 return 0x00000000U;
327}
328static inline u32 sim_send_ring_addr_lo__init_f(void)
329{
330 return 0x0U;
331}
332static inline u32 sim_send_ring_addr_lo__prod_v(void)
333{
334 return 0x00000000U;
335}
336static inline u32 sim_send_ring_addr_lo__prod_f(void)
337{
338 return 0x0U;
339}
340static inline u32 sim_send_ring_hi_r(void)
341{
342 return 0x00000004U;
343}
344static inline u32 sim_send_ring_hi_addr_s(void)
345{
346 return 20U;
347}
348static inline u32 sim_send_ring_hi_addr_f(u32 v)
349{
350 return (v & 0xfffffU) << 0U;
351}
352static inline u32 sim_send_ring_hi_addr_m(void)
353{
354 return 0xfffffU << 0U;
355}
356static inline u32 sim_send_ring_hi_addr_v(u32 r)
357{
358 return (r >> 0U) & 0xfffffU;
359}
360static inline u32 sim_send_ring_hi_addr__init_v(void)
361{
362 return 0x00000000U;
363}
364static inline u32 sim_send_ring_hi_addr__init_f(void)
365{
366 return 0x0U;
367}
368static inline u32 sim_send_ring_hi_addr__prod_v(void)
369{
370 return 0x00000000U;
371}
372static inline u32 sim_send_ring_hi_addr__prod_f(void)
373{
374 return 0x0U;
375}
376static inline u32 sim_send_put_r(void)
377{
378 return 0x00000008U;
379}
380static inline u32 sim_send_put_pointer_s(void)
381{
382 return 29U;
383}
384static inline u32 sim_send_put_pointer_f(u32 v)
385{
386 return (v & 0x1fffffffU) << 3U;
387}
388static inline u32 sim_send_put_pointer_m(void)
389{
390 return 0x1fffffffU << 3U;
391}
392static inline u32 sim_send_put_pointer_v(u32 r)
393{
394 return (r >> 3U) & 0x1fffffffU;
395}
396static inline u32 sim_send_get_r(void)
397{
398 return 0x0000000cU;
399}
400static inline u32 sim_send_get_pointer_s(void)
401{
402 return 29U;
403}
404static inline u32 sim_send_get_pointer_f(u32 v)
405{
406 return (v & 0x1fffffffU) << 3U;
407}
408static inline u32 sim_send_get_pointer_m(void)
409{
410 return 0x1fffffffU << 3U;
411}
412static inline u32 sim_send_get_pointer_v(u32 r)
413{
414 return (r >> 3U) & 0x1fffffffU;
415}
416static inline u32 sim_recv_ring_r(void)
417{
418 return 0x00000010U;
419}
420static inline u32 sim_recv_ring_target_s(void)
421{
422 return 2U;
423}
424static inline u32 sim_recv_ring_target_f(u32 v)
425{
426 return (v & 0x3U) << 0U;
427}
428static inline u32 sim_recv_ring_target_m(void)
429{
430 return 0x3U << 0U;
431}
432static inline u32 sim_recv_ring_target_v(u32 r)
433{
434 return (r >> 0) & 0x3U;
435}
436static inline u32 sim_recv_ring_target_phys_init_v(void)
437{
438 return 0x00000001U;
439}
440static inline u32 sim_recv_ring_target_phys_init_f(void)
441{
442 return 0x1U;
443}
444static inline u32 sim_recv_ring_target_phys__init_v(void)
445{
446 return 0x00000001U;
447}
448static inline u32 sim_recv_ring_target_phys__init_f(void)
449{
450 return 0x1U;
451}
452static inline u32 sim_recv_ring_target_phys__prod_v(void)
453{
454 return 0x00000001U;
455}
456static inline u32 sim_recv_ring_target_phys__prod_f(void)
457{
458 return 0x1U;
459}
460static inline u32 sim_recv_ring_target_phys_nvm_v(void)
461{
462 return 0x00000001U;
463}
464static inline u32 sim_recv_ring_target_phys_nvm_f(void)
465{
466 return 0x1U;
467}
468static inline u32 sim_recv_ring_target_phys_pci_v(void)
469{
470 return 0x00000002U;
471}
472static inline u32 sim_recv_ring_target_phys_pci_f(void)
473{
474 return 0x2U;
475}
476static inline u32 sim_recv_ring_target_phys_pci_coherent_v(void)
477{
478 return 0x00000003U;
479}
480static inline u32 sim_recv_ring_target_phys_pci_coherent_f(void)
481{
482 return 0x3U;
483}
484static inline u32 sim_recv_ring_status_s(void)
485{
486 return 1U;
487}
488static inline u32 sim_recv_ring_status_f(u32 v)
489{
490 return (v & 0x1U) << 3U;
491}
492static inline u32 sim_recv_ring_status_m(void)
493{
494 return 0x1U << 3U;
495}
496static inline u32 sim_recv_ring_status_v(u32 r)
497{
498 return (r >> 3U) & 0x1U;
499}
500static inline u32 sim_recv_ring_status_init_v(void)
501{
502 return 0x00000000U;
503}
504static inline u32 sim_recv_ring_status_init_f(void)
505{
506 return 0x0U;
507}
508static inline u32 sim_recv_ring_status__init_v(void)
509{
510 return 0x00000000U;
511}
512static inline u32 sim_recv_ring_status__init_f(void)
513{
514 return 0x0U;
515}
516static inline u32 sim_recv_ring_status__prod_v(void)
517{
518 return 0x00000000U;
519}
520static inline u32 sim_recv_ring_status__prod_f(void)
521{
522 return 0x0U;
523}
524static inline u32 sim_recv_ring_status_invalid_v(void)
525{
526 return 0x00000000U;
527}
528static inline u32 sim_recv_ring_status_invalid_f(void)
529{
530 return 0x0U;
531}
532static inline u32 sim_recv_ring_status_valid_v(void)
533{
534 return 0x00000001U;
535}
536static inline u32 sim_recv_ring_status_valid_f(void)
537{
538 return 0x8U;
539}
540static inline u32 sim_recv_ring_size_s(void)
541{
542 return 2U;
543}
544static inline u32 sim_recv_ring_size_f(u32 v)
545{
546 return (v & 0x3U) << 4U;
547}
548static inline u32 sim_recv_ring_size_m(void)
549{
550 return 0x3U << 4U;
551}
552static inline u32 sim_recv_ring_size_v(u32 r)
553{
554 return (r >> 4U) & 0x3U;
555}
556static inline u32 sim_recv_ring_size_init_v(void)
557{
558 return 0x00000000U;
559}
560static inline u32 sim_recv_ring_size_init_f(void)
561{
562 return 0x0U;
563}
564static inline u32 sim_recv_ring_size__init_v(void)
565{
566 return 0x00000000U;
567}
568static inline u32 sim_recv_ring_size__init_f(void)
569{
570 return 0x0U;
571}
572static inline u32 sim_recv_ring_size__prod_v(void)
573{
574 return 0x00000000U;
575}
576static inline u32 sim_recv_ring_size__prod_f(void)
577{
578 return 0x0U;
579}
580static inline u32 sim_recv_ring_size_4kb_v(void)
581{
582 return 0x00000000U;
583}
584static inline u32 sim_recv_ring_size_4kb_f(void)
585{
586 return 0x0U;
587}
588static inline u32 sim_recv_ring_size_8kb_v(void)
589{
590 return 0x00000001U;
591}
592static inline u32 sim_recv_ring_size_8kb_f(void)
593{
594 return 0x10U;
595}
596static inline u32 sim_recv_ring_size_12kb_v(void)
597{
598 return 0x00000002U;
599}
600static inline u32 sim_recv_ring_size_12kb_f(void)
601{
602 return 0x20U;
603}
604static inline u32 sim_recv_ring_size_16kb_v(void)
605{
606 return 0x00000003U;
607}
608static inline u32 sim_recv_ring_size_16kb_f(void)
609{
610 return 0x30U;
611}
612static inline u32 sim_recv_ring_gp_in_ring_s(void)
613{
614 return 1U;
615}
616static inline u32 sim_recv_ring_gp_in_ring_f(u32 v)
617{
618 return (v & 0x1U) << 11U;
619}
620static inline u32 sim_recv_ring_gp_in_ring_m(void)
621{
622 return 0x1U << 11U;
623}
624static inline u32 sim_recv_ring_gp_in_ring_v(u32 r)
625{
626 return (r >> 11U) & 0x1U;
627}
628static inline u32 sim_recv_ring_gp_in_ring__init_v(void)
629{
630 return 0x00000000U;
631}
632static inline u32 sim_recv_ring_gp_in_ring__init_f(void)
633{
634 return 0x0U;
635}
636static inline u32 sim_recv_ring_gp_in_ring__prod_v(void)
637{
638 return 0x00000000U;
639}
640static inline u32 sim_recv_ring_gp_in_ring__prod_f(void)
641{
642 return 0x0U;
643}
644static inline u32 sim_recv_ring_gp_in_ring_no_v(void)
645{
646 return 0x00000000U;
647}
648static inline u32 sim_recv_ring_gp_in_ring_no_f(void)
649{
650 return 0x0U;
651}
652static inline u32 sim_recv_ring_gp_in_ring_yes_v(void)
653{
654 return 0x00000001U;
655}
656static inline u32 sim_recv_ring_gp_in_ring_yes_f(void)
657{
658 return 0x800U;
659}
660static inline u32 sim_recv_ring_addr_lo_s(void)
661{
662 return 20U;
663}
664static inline u32 sim_recv_ring_addr_lo_f(u32 v)
665{
666 return (v & 0xfffffU) << 12U;
667}
668static inline u32 sim_recv_ring_addr_lo_m(void)
669{
670 return 0xfffffU << 12U;
671}
672static inline u32 sim_recv_ring_addr_lo_v(u32 r)
673{
674 return (r >> 12U) & 0xfffffU;
675}
676static inline u32 sim_recv_ring_addr_lo__init_v(void)
677{
678 return 0x00000000U;
679}
680static inline u32 sim_recv_ring_addr_lo__init_f(void)
681{
682 return 0x0U;
683}
684static inline u32 sim_recv_ring_addr_lo__prod_v(void)
685{
686 return 0x00000000U;
687}
688static inline u32 sim_recv_ring_addr_lo__prod_f(void)
689{
690 return 0x0U;
691}
692static inline u32 sim_recv_ring_hi_r(void)
693{
694 return 0x00000014U;
695}
696static inline u32 sim_recv_ring_hi_addr_s(void)
697{
698 return 20U;
699}
700static inline u32 sim_recv_ring_hi_addr_f(u32 v)
701{
702 return (v & 0xfffffU) << 0U;
703}
704static inline u32 sim_recv_ring_hi_addr_m(void)
705{
706 return 0xfffffU << 0U;
707}
708static inline u32 sim_recv_ring_hi_addr_v(u32 r)
709{
710 return (r >> 0U) & 0xfffffU;
711}
712static inline u32 sim_recv_ring_hi_addr__init_v(void)
713{
714 return 0x00000000U;
715}
716static inline u32 sim_recv_ring_hi_addr__init_f(void)
717{
718 return 0x0U;
719}
720static inline u32 sim_recv_ring_hi_addr__prod_v(void)
721{
722 return 0x00000000U;
723}
724static inline u32 sim_recv_ring_hi_addr__prod_f(void)
725{
726 return 0x0U;
727}
728static inline u32 sim_recv_put_r(void)
729{
730 return 0x00000018U;
731}
732static inline u32 sim_recv_put_pointer_s(void)
733{
734 return 11U;
735}
736static inline u32 sim_recv_put_pointer_f(u32 v)
737{
738 return (v & 0x7ffU) << 3U;
739}
740static inline u32 sim_recv_put_pointer_m(void)
741{
742 return 0x7ffU << 3U;
743}
744static inline u32 sim_recv_put_pointer_v(u32 r)
745{
746 return (r >> 3U) & 0x7ffU;
747}
748static inline u32 sim_recv_get_r(void)
749{
750 return 0x0000001cU;
751}
752static inline u32 sim_recv_get_pointer_s(void)
753{
754 return 11U;
755}
756static inline u32 sim_recv_get_pointer_f(u32 v)
757{
758 return (v & 0x7ffU) << 3U;
759}
760static inline u32 sim_recv_get_pointer_m(void)
761{
762 return 0x7ffU << 3U;
763}
764static inline u32 sim_recv_get_pointer_v(u32 r)
765{
766 return (r >> 3U) & 0x7ffU;
767}
768static inline u32 sim_config_r(void)
769{
770 return 0x00000020U;
771}
772static inline u32 sim_config_mode_s(void)
773{
774 return 1U;
775}
776static inline u32 sim_config_mode_f(u32 v)
777{
778 return (v & 0x1U) << 0U;
779}
780static inline u32 sim_config_mode_m(void)
781{
782 return 0x1U << 0U;
783}
784static inline u32 sim_config_mode_v(u32 r)
785{
786 return (r >> 0U) & 0x1U;
787}
788static inline u32 sim_config_mode_disabled_v(void)
789{
790 return 0x00000000U;
791}
792static inline u32 sim_config_mode_disabled_f(void)
793{
794 return 0x0U;
795}
796static inline u32 sim_config_mode_enabled_v(void)
797{
798 return 0x00000001U;
799}
800static inline u32 sim_config_mode_enabled_f(void)
801{
802 return 0x1U;
803}
804static inline u32 sim_config_channels_s(void)
805{
806 return 7U;
807}
808static inline u32 sim_config_channels_f(u32 v)
809{
810 return (v & 0x7fU) << 1U;
811}
812static inline u32 sim_config_channels_m(void)
813{
814 return 0x7fU << 1U;
815}
816static inline u32 sim_config_channels_v(u32 r)
817{
818 return (r >> 1U) & 0x7fU;
819}
820static inline u32 sim_config_channels_none_v(void)
821{
822 return 0x00000000U;
823}
824static inline u32 sim_config_channels_none_f(void)
825{
826 return 0x0U;
827}
828static inline u32 sim_config_cached_only_s(void)
829{
830 return 1U;
831}
832static inline u32 sim_config_cached_only_f(u32 v)
833{
834 return (v & 0x1U) << 8U;
835}
836static inline u32 sim_config_cached_only_m(void)
837{
838 return 0x1U << 8U;
839}
840static inline u32 sim_config_cached_only_v(u32 r)
841{
842 return (r >> 8U) & 0x1U;
843}
844static inline u32 sim_config_cached_only_disabled_v(void)
845{
846 return 0x00000000U;
847}
848static inline u32 sim_config_cached_only_disabled_f(void)
849{
850 return 0x0U;
851}
852static inline u32 sim_config_cached_only_enabled_v(void)
853{
854 return 0x00000001U;
855}
856static inline u32 sim_config_cached_only_enabled_f(void)
857{
858 return 0x100U;
859}
860static inline u32 sim_config_validity_s(void)
861{
862 return 2U;
863}
864static inline u32 sim_config_validity_f(u32 v)
865{
866 return (v & 0x3U) << 9U;
867}
868static inline u32 sim_config_validity_m(void)
869{
870 return 0x3U << 9U;
871}
872static inline u32 sim_config_validity_v(u32 r)
873{
874 return (r >> 9U) & 0x3U;
875}
876static inline u32 sim_config_validity__init_v(void)
877{
878 return 0x00000001U;
879}
880static inline u32 sim_config_validity__init_f(void)
881{
882 return 0x200U;
883}
884static inline u32 sim_config_validity_valid_v(void)
885{
886 return 0x00000001U;
887}
888static inline u32 sim_config_validity_valid_f(void)
889{
890 return 0x200U;
891}
892static inline u32 sim_config_simulation_s(void)
893{
894 return 2U;
895}
896static inline u32 sim_config_simulation_f(u32 v)
897{
898 return (v & 0x3U) << 12U;
899}
900static inline u32 sim_config_simulation_m(void)
901{
902 return 0x3U << 12U;
903}
904static inline u32 sim_config_simulation_v(u32 r)
905{
906 return (r >> 12U) & 0x3U;
907}
908static inline u32 sim_config_simulation_disabled_v(void)
909{
910 return 0x00000000U;
911}
912static inline u32 sim_config_simulation_disabled_f(void)
913{
914 return 0x0U;
915}
916static inline u32 sim_config_simulation_fmodel_v(void)
917{
918 return 0x00000001U;
919}
920static inline u32 sim_config_simulation_fmodel_f(void)
921{
922 return 0x1000U;
923}
924static inline u32 sim_config_simulation_rtlsim_v(void)
925{
926 return 0x00000002U;
927}
928static inline u32 sim_config_simulation_rtlsim_f(void)
929{
930 return 0x2000U;
931}
932static inline u32 sim_config_secondary_display_s(void)
933{
934 return 1U;
935}
936static inline u32 sim_config_secondary_display_f(u32 v)
937{
938 return (v & 0x1U) << 14U;
939}
940static inline u32 sim_config_secondary_display_m(void)
941{
942 return 0x1U << 14U;
943}
944static inline u32 sim_config_secondary_display_v(u32 r)
945{
946 return (r >> 14U) & 0x1U;
947}
948static inline u32 sim_config_secondary_display_disabled_v(void)
949{
950 return 0x00000000U;
951}
952static inline u32 sim_config_secondary_display_disabled_f(void)
953{
954 return 0x0U;
955}
956static inline u32 sim_config_secondary_display_enabled_v(void)
957{
958 return 0x00000001U;
959}
960static inline u32 sim_config_secondary_display_enabled_f(void)
961{
962 return 0x4000U;
963}
964static inline u32 sim_config_num_heads_s(void)
965{
966 return 8U;
967}
968static inline u32 sim_config_num_heads_f(u32 v)
969{
970 return (v & 0xffU) << 17U;
971}
972static inline u32 sim_config_num_heads_m(void)
973{
974 return 0xffU << 17U;
975}
976static inline u32 sim_config_num_heads_v(u32 r)
977{
978 return (r >> 17U) & 0xffU;
979}
980static inline u32 sim_event_ring_r(void)
981{
982 return 0x00000030U;
983}
984static inline u32 sim_event_ring_target_s(void)
985{
986 return 2U;
987}
988static inline u32 sim_event_ring_target_f(u32 v)
989{
990 return (v & 0x3U) << 0U;
991}
992static inline u32 sim_event_ring_target_m(void)
993{
994 return 0x3U << 0U;
995}
996static inline u32 sim_event_ring_target_v(u32 r)
997{
998 return (r >> 0U) & 0x3U;
999}
1000static inline u32 sim_event_ring_target_phys_init_v(void)
1001{
1002 return 0x00000001U;
1003}
1004static inline u32 sim_event_ring_target_phys_init_f(void)
1005{
1006 return 0x1U;
1007}
1008static inline u32 sim_event_ring_target_phys__init_v(void)
1009{
1010 return 0x00000001U;
1011}
1012static inline u32 sim_event_ring_target_phys__init_f(void)
1013{
1014 return 0x1U;
1015}
1016static inline u32 sim_event_ring_target_phys__prod_v(void)
1017{
1018 return 0x00000001U;
1019}
1020static inline u32 sim_event_ring_target_phys__prod_f(void)
1021{
1022 return 0x1U;
1023}
1024static inline u32 sim_event_ring_target_phys_nvm_v(void)
1025{
1026 return 0x00000001U;
1027}
1028static inline u32 sim_event_ring_target_phys_nvm_f(void)
1029{
1030 return 0x1U;
1031}
1032static inline u32 sim_event_ring_target_phys_pci_v(void)
1033{
1034 return 0x00000002U;
1035}
1036static inline u32 sim_event_ring_target_phys_pci_f(void)
1037{
1038 return 0x2U;
1039}
1040static inline u32 sim_event_ring_target_phys_pci_coherent_v(void)
1041{
1042 return 0x00000003U;
1043}
1044static inline u32 sim_event_ring_target_phys_pci_coherent_f(void)
1045{
1046 return 0x3U;
1047}
1048static inline u32 sim_event_ring_status_s(void)
1049{
1050 return 1U;
1051}
1052static inline u32 sim_event_ring_status_f(u32 v)
1053{
1054 return (v & 0x1U) << 3U;
1055}
1056static inline u32 sim_event_ring_status_m(void)
1057{
1058 return 0x1U << 3U;
1059}
1060static inline u32 sim_event_ring_status_v(u32 r)
1061{
1062 return (r >> 3U) & 0x1U;
1063}
1064static inline u32 sim_event_ring_status_init_v(void)
1065{
1066 return 0x00000000U;
1067}
1068static inline u32 sim_event_ring_status_init_f(void)
1069{
1070 return 0x0U;
1071}
1072static inline u32 sim_event_ring_status__init_v(void)
1073{
1074 return 0x00000000U;
1075}
1076static inline u32 sim_event_ring_status__init_f(void)
1077{
1078 return 0x0U;
1079}
1080static inline u32 sim_event_ring_status__prod_v(void)
1081{
1082 return 0x00000000U;
1083}
1084static inline u32 sim_event_ring_status__prod_f(void)
1085{
1086 return 0x0U;
1087}
1088static inline u32 sim_event_ring_status_invalid_v(void)
1089{
1090 return 0x00000000U;
1091}
1092static inline u32 sim_event_ring_status_invalid_f(void)
1093{
1094 return 0x0U;
1095}
1096static inline u32 sim_event_ring_status_valid_v(void)
1097{
1098 return 0x00000001U;
1099}
1100static inline u32 sim_event_ring_status_valid_f(void)
1101{
1102 return 0x8U;
1103}
1104static inline u32 sim_event_ring_size_s(void)
1105{
1106 return 2U;
1107}
1108static inline u32 sim_event_ring_size_f(u32 v)
1109{
1110 return (v & 0x3U) << 4U;
1111}
1112static inline u32 sim_event_ring_size_m(void)
1113{
1114 return 0x3U << 4U;
1115}
1116static inline u32 sim_event_ring_size_v(u32 r)
1117{
1118 return (r >> 4U) & 0x3U;
1119}
1120static inline u32 sim_event_ring_size_init_v(void)
1121{
1122 return 0x00000000U;
1123}
1124static inline u32 sim_event_ring_size_init_f(void)
1125{
1126 return 0x0U;
1127}
1128static inline u32 sim_event_ring_size__init_v(void)
1129{
1130 return 0x00000000U;
1131}
1132static inline u32 sim_event_ring_size__init_f(void)
1133{
1134 return 0x0U;
1135}
1136static inline u32 sim_event_ring_size__prod_v(void)
1137{
1138 return 0x00000000U;
1139}
1140static inline u32 sim_event_ring_size__prod_f(void)
1141{
1142 return 0x0U;
1143}
1144static inline u32 sim_event_ring_size_4kb_v(void)
1145{
1146 return 0x00000000U;
1147}
1148static inline u32 sim_event_ring_size_4kb_f(void)
1149{
1150 return 0x0U;
1151}
1152static inline u32 sim_event_ring_size_8kb_v(void)
1153{
1154 return 0x00000001U;
1155}
1156static inline u32 sim_event_ring_size_8kb_f(void)
1157{
1158 return 0x10U;
1159}
1160static inline u32 sim_event_ring_size_12kb_v(void)
1161{
1162 return 0x00000002U;
1163}
1164static inline u32 sim_event_ring_size_12kb_f(void)
1165{
1166 return 0x20U;
1167}
1168static inline u32 sim_event_ring_size_16kb_v(void)
1169{
1170 return 0x00000003U;
1171}
1172static inline u32 sim_event_ring_size_16kb_f(void)
1173{
1174 return 0x30U;
1175}
1176static inline u32 sim_event_ring_gp_in_ring_s(void)
1177{
1178 return 1U;
1179}
1180static inline u32 sim_event_ring_gp_in_ring_f(u32 v)
1181{
1182 return (v & 0x1U) << 11U;
1183}
1184static inline u32 sim_event_ring_gp_in_ring_m(void)
1185{
1186 return 0x1U << 11U;
1187}
1188static inline u32 sim_event_ring_gp_in_ring_v(u32 r)
1189{
1190 return (r >> 11U) & 0x1U;
1191}
1192static inline u32 sim_event_ring_gp_in_ring__init_v(void)
1193{
1194 return 0x00000000U;
1195}
1196static inline u32 sim_event_ring_gp_in_ring__init_f(void)
1197{
1198 return 0x0U;
1199}
1200static inline u32 sim_event_ring_gp_in_ring__prod_v(void)
1201{
1202 return 0x00000000U;
1203}
1204static inline u32 sim_event_ring_gp_in_ring__prod_f(void)
1205{
1206 return 0x0U;
1207}
1208static inline u32 sim_event_ring_gp_in_ring_no_v(void)
1209{
1210 return 0x00000000U;
1211}
1212static inline u32 sim_event_ring_gp_in_ring_no_f(void)
1213{
1214 return 0x0U;
1215}
1216static inline u32 sim_event_ring_gp_in_ring_yes_v(void)
1217{
1218 return 0x00000001U;
1219}
1220static inline u32 sim_event_ring_gp_in_ring_yes_f(void)
1221{
1222 return 0x800U;
1223}
1224static inline u32 sim_event_ring_addr_lo_s(void)
1225{
1226 return 20U;
1227}
1228static inline u32 sim_event_ring_addr_lo_f(u32 v)
1229{
1230 return (v & 0xfffffU) << 12U;
1231}
1232static inline u32 sim_event_ring_addr_lo_m(void)
1233{
1234 return 0xfffffU << 12U;
1235}
1236static inline u32 sim_event_ring_addr_lo_v(u32 r)
1237{
1238 return (r >> 12U) & 0xfffffU;
1239}
1240static inline u32 sim_event_ring_addr_lo__init_v(void)
1241{
1242 return 0x00000000U;
1243}
1244static inline u32 sim_event_ring_addr_lo__init_f(void)
1245{
1246 return 0x0U;
1247}
1248static inline u32 sim_event_ring_addr_lo__prod_v(void)
1249{
1250 return 0x00000000U;
1251}
1252static inline u32 sim_event_ring_addr_lo__prod_f(void)
1253{
1254 return 0x0U;
1255}
1256static inline u32 sim_event_ring_hi_v(void)
1257{
1258 return 0x00000034U;
1259}
1260static inline u32 sim_event_ring_hi_addr_s(void)
1261{
1262 return 20U;
1263}
1264static inline u32 sim_event_ring_hi_addr_f(u32 v)
1265{
1266 return (v & 0xfffffU) << 0U;
1267}
1268static inline u32 sim_event_ring_hi_addr_m(void)
1269{
1270 return 0xfffffU << 0U;
1271}
1272static inline u32 sim_event_ring_hi_addr_v(u32 r)
1273{
1274 return (r >> 0U) & 0xfffffU;
1275}
1276static inline u32 sim_event_ring_hi_addr__init_v(void)
1277{
1278 return 0x00000000U;
1279}
1280static inline u32 sim_event_ring_hi_addr__init_f(void)
1281{
1282 return 0x0U;
1283}
1284static inline u32 sim_event_ring_hi_addr__prod_v(void)
1285{
1286 return 0x00000000U;
1287}
1288static inline u32 sim_event_ring_hi_addr__prod_f(void)
1289{
1290 return 0x0U;
1291}
1292static inline u32 sim_event_put_r(void)
1293{
1294 return 0x00000038U;
1295}
1296static inline u32 sim_event_put_pointer_s(void)
1297{
1298 return 30U;
1299}
1300static inline u32 sim_event_put_pointer_f(u32 v)
1301{
1302 return (v & 0x3fffffffU) << 2U;
1303}
1304static inline u32 sim_event_put_pointer_m(void)
1305{
1306 return 0x3fffffffU << 2U;
1307}
1308static inline u32 sim_event_put_pointer_v(u32 r)
1309{
1310 return (r >> 2U) & 0x3fffffffU;
1311}
1312static inline u32 sim_event_get_r(void)
1313{
1314 return 0x0000003cU;
1315}
1316static inline u32 sim_event_get_pointer_s(void)
1317{
1318 return 30U;
1319}
1320static inline u32 sim_event_get_pointer_f(u32 v)
1321{
1322 return (v & 0x3fffffffU) << 2U;
1323}
1324static inline u32 sim_event_get_pointer_m(void)
1325{
1326 return 0x3fffffffU << 2U;
1327}
1328static inline u32 sim_event_get_pointer_v(u32 r)
1329{
1330 return (r >> 2U) & 0x3fffffffU;
1331}
1332static inline u32 sim_status_r(void)
1333{
1334 return 0x00000028U;
1335}
1336static inline u32 sim_status_send_put_s(void)
1337{
1338 return 1U;
1339}
1340static inline u32 sim_status_send_put_f(u32 v)
1341{
1342 return (v & 0x1U) << 0U;
1343}
1344static inline u32 sim_status_send_put_m(void)
1345{
1346 return 0x1 << 0U;
1347}
1348static inline u32 sim_status_send_put_v(u32 r)
1349{
1350 return (r >> 0U) & 0x1U;
1351}
1352static inline u32 sim_status_send_put__init_v(void)
1353{
1354 return 0x00000000U;
1355}
1356static inline u32 sim_status_send_put__init_f(void)
1357{
1358 return 0x0U;
1359}
1360static inline u32 sim_status_send_put_idle_v(void)
1361{
1362 return 0x00000000U;
1363}
1364static inline u32 sim_status_send_put_idle_f(void)
1365{
1366 return 0x0U;
1367}
1368static inline u32 sim_status_send_put_pending_v(void)
1369{
1370 return 0x00000001U;
1371}
1372static inline u32 sim_status_send_put_pending_f(void)
1373{
1374 return 0x1U;
1375}
1376static inline u32 sim_status_send_get_s(void)
1377{
1378 return 1U;
1379}
1380static inline u32 sim_status_send_get_f(u32 v)
1381{
1382 return (v & 0x1U) << 1U;
1383}
1384static inline u32 sim_status_send_get_m(void)
1385{
1386 return 0x1U << 1U;
1387}
1388static inline u32 sim_status_send_get_v(u32 r)
1389{
1390 return (r >> 1U) & 0x1U;
1391}
1392static inline u32 sim_status_send_get__init_v(void)
1393{
1394 return 0x00000000U;
1395}
1396static inline u32 sim_status_send_get__init_f(void)
1397{
1398 return 0x0U;
1399}
1400static inline u32 sim_status_send_get_idle_v(void)
1401{
1402 return 0x00000000U;
1403}
1404static inline u32 sim_status_send_get_idle_f(void)
1405{
1406 return 0x0U;
1407}
1408static inline u32 sim_status_send_get_pending_v(void)
1409{
1410 return 0x00000001U;
1411}
1412static inline u32 sim_status_send_get_pending_f(void)
1413{
1414 return 0x2U;
1415}
1416static inline u32 sim_status_send_get_clear_v(void)
1417{
1418 return 0x00000001U;
1419}
1420static inline u32 sim_status_send_get_clear_f(void)
1421{
1422 return 0x2U;
1423}
1424static inline u32 sim_status_recv_put_s(void)
1425{
1426 return 1U;
1427}
1428static inline u32 sim_status_recv_put_f(u32 v)
1429{
1430 return (v & 0x1U) << 2U;
1431}
1432static inline u32 sim_status_recv_put_m(void)
1433{
1434 return 0x1U << 2U;
1435}
1436static inline u32 sim_status_recv_put_v(u32 r)
1437{
1438 return (r >> 2U) & 0x1U;
1439}
1440static inline u32 sim_status_recv_put__init_v(void)
1441{
1442 return 0x00000000U;
1443}
1444static inline u32 sim_status_recv_put__init_f(void)
1445{
1446 return 0x0U;
1447}
1448static inline u32 sim_status_recv_put_idle_v(void)
1449{
1450 return 0x00000000U;
1451}
1452static inline u32 sim_status_recv_put_idle_f(void)
1453{
1454 return 0x0U;
1455}
1456static inline u32 sim_status_recv_put_pending_v(void)
1457{
1458 return 0x00000001U;
1459}
1460static inline u32 sim_status_recv_put_pending_f(void)
1461{
1462 return 0x4U;
1463}
1464static inline u32 sim_status_recv_put_clear_v(void)
1465{
1466 return 0x00000001U;
1467}
1468static inline u32 sim_status_recv_put_clear_f(void)
1469{
1470 return 0x4U;
1471}
1472static inline u32 sim_status_recv_get_s(void)
1473{
1474 return 1U;
1475}
1476static inline u32 sim_status_recv_get_f(u32 v)
1477{
1478 return (v & 0x1U) << 3U;
1479}
1480static inline u32 sim_status_recv_get_m(void)
1481{
1482 return 0x1U << 3U;
1483}
1484static inline u32 sim_status_recv_get_v(u32 r)
1485{
1486 return (r >> 3U) & 0x1U;
1487}
1488static inline u32 sim_status_recv_get__init_v(void)
1489{
1490 return 0x00000000U;
1491}
1492static inline u32 sim_status_recv_get__init_f(void)
1493{
1494 return 0x0U;
1495}
1496static inline u32 sim_status_recv_get_idle_v(void)
1497{
1498 return 0x00000000U;
1499}
1500static inline u32 sim_status_recv_get_idle_f(void)
1501{
1502 return 0x0U;
1503}
1504static inline u32 sim_status_recv_get_pending_v(void)
1505{
1506 return 0x00000001U;
1507}
1508static inline u32 sim_status_recv_get_pending_f(void)
1509{
1510 return 0x8U;
1511}
1512static inline u32 sim_status_event_put_s(void)
1513{
1514 return 1U;
1515}
1516static inline u32 sim_status_event_put_f(u32 v)
1517{
1518 return (v & 0x1U) << 4U;
1519}
1520static inline u32 sim_status_event_put_m(void)
1521{
1522 return 0x1U << 4U;
1523}
1524static inline u32 sim_status_event_put_v(u32 r)
1525{
1526 return (r >> 4U) & 0x1U;
1527}
1528static inline u32 sim_status_event_put__init_v(void)
1529{
1530 return 0x00000000U;
1531}
1532static inline u32 sim_status_event_put__init_f(void)
1533{
1534 return 0x0U;
1535}
1536static inline u32 sim_status_event_put_idle_v(void)
1537{
1538 return 0x00000000U;
1539}
1540static inline u32 sim_status_event_put_idle_f(void)
1541{
1542 return 0x0U;
1543}
1544static inline u32 sim_status_event_put_pending_v(void)
1545{
1546 return 0x00000001U;
1547}
1548static inline u32 sim_status_event_put_pending_f(void)
1549{
1550 return 0x10U;
1551}
1552static inline u32 sim_status_event_put_clear_v(void)
1553{
1554 return 0x00000001U;
1555}
1556static inline u32 sim_status_event_put_clear_f(void)
1557{
1558 return 0x10U;
1559}
1560static inline u32 sim_status_event_get_s(void)
1561{
1562 return 1U;
1563}
1564static inline u32 sim_status_event_get_f(u32 v)
1565{
1566 return (v & 0x1U) << 5U;
1567}
1568static inline u32 sim_status_event_get_m(void)
1569{
1570 return 0x1U << 5U;
1571}
1572static inline u32 sim_status_event_get_v(u32 r)
1573{
1574 return (r >> 5U) & 0x1U;
1575}
1576static inline u32 sim_status_event_get__init_v(void)
1577{
1578 return 0x00000000U;
1579}
1580static inline u32 sim_status_event_get__init_f(void)
1581{
1582 return 0x0U;
1583}
1584static inline u32 sim_status_event_get_idle_v(void)
1585{
1586 return 0x00000000U;
1587}
1588static inline u32 sim_status_event_get_idle_f(void)
1589{
1590 return 0x0U;
1591}
1592static inline u32 sim_status_event_get_pending_v(void)
1593{
1594 return 0x00000001U;
1595}
1596static inline u32 sim_status_event_get_pending_f(void)
1597{
1598 return 0x20U;
1599}
1600static inline u32 sim_control_r(void)
1601{
1602 return 0x0000002cU;
1603}
1604static inline u32 sim_control_send_put_s(void)
1605{
1606 return 1U;
1607}
1608static inline u32 sim_control_send_put_f(u32 v)
1609{
1610 return (v & 0x1U) << 0U;
1611}
1612static inline u32 sim_control_send_put_m(void)
1613{
1614 return 0x1U << 0U;
1615}
1616static inline u32 sim_control_send_put_v(u32 r)
1617{
1618 return (r >> 0U) & 0x1U;
1619}
1620static inline u32 sim_control_send_put__init_v(void)
1621{
1622 return 0x00000000U;
1623}
1624static inline u32 sim_control_send_put__init_f(void)
1625{
1626 return 0x0U;
1627}
1628static inline u32 sim_control_send_put_disabled_v(void)
1629{
1630 return 0x00000000U;
1631}
1632static inline u32 sim_control_send_put_disabled_f(void)
1633{
1634 return 0x0U;
1635}
1636static inline u32 sim_control_send_put_enabled_v(void)
1637{
1638 return 0x00000001U;
1639}
1640static inline u32 sim_control_send_put_enabled_f(void)
1641{
1642 return 0x1U;
1643}
1644static inline u32 sim_control_send_get_s(void)
1645{
1646 return 1U;
1647}
1648static inline u32 sim_control_send_get_f(u32 v)
1649{
1650 return (v & 0x1U) << 1U;
1651}
1652static inline u32 sim_control_send_get_m(void)
1653{
1654 return 0x1U << 1U;
1655}
1656static inline u32 sim_control_send_get_v(u32 r)
1657{
1658 return (r >> 1U) & 0x1U;
1659}
1660static inline u32 sim_control_send_get__init_v(void)
1661{
1662 return 0x00000000U;
1663}
1664static inline u32 sim_control_send_get__init_f(void)
1665{
1666 return 0x0U;
1667}
1668static inline u32 sim_control_send_get_disabled_v(void)
1669{
1670 return 0x00000000U;
1671}
1672static inline u32 sim_control_send_get_disabled_f(void)
1673{
1674 return 0x0U;
1675}
1676static inline u32 sim_control_send_get_enabled_v(void)
1677{
1678 return 0x00000001U;
1679}
1680static inline u32 sim_control_send_get_enabled_f(void)
1681{
1682 return 0x2U;
1683}
1684static inline u32 sim_control_recv_put_s(void)
1685{
1686 return 1U;
1687}
1688static inline u32 sim_control_recv_put_f(u32 v)
1689{
1690 return (v & 0x1U) << 2U;
1691}
1692static inline u32 sim_control_recv_put_m(void)
1693{
1694 return 0x1U << 2U;
1695}
1696static inline u32 sim_control_recv_put_v(u32 r)
1697{
1698 return (r >> 2U) & 0x1U;
1699}
1700static inline u32 sim_control_recv_put__init_v(void)
1701{
1702 return 0x00000000U;
1703}
1704static inline u32 sim_control_recv_put__init_f(void)
1705{
1706 return 0x0U;
1707}
1708static inline u32 sim_control_recv_put_disabled_v(void)
1709{
1710 return 0x00000000U;
1711}
1712static inline u32 sim_control_recv_put_disabled_f(void)
1713{
1714 return 0x0U;
1715}
1716static inline u32 sim_control_recv_put_enabled_v(void)
1717{
1718 return 0x00000001U;
1719}
1720static inline u32 sim_control_recv_put_enabled_f(void)
1721{
1722 return 0x4U;
1723}
1724static inline u32 sim_control_recv_get_s(void)
1725{
1726 return 1U;
1727}
1728static inline u32 sim_control_recv_get_f(u32 v)
1729{
1730 return (v & 0x1U) << 3U;
1731}
1732static inline u32 sim_control_recv_get_m(void)
1733{
1734 return 0x1U << 3U;
1735}
1736static inline u32 sim_control_recv_get_v(u32 r)
1737{
1738 return (r >> 3U) & 0x1U;
1739}
1740static inline u32 sim_control_recv_get__init_v(void)
1741{
1742 return 0x00000000U;
1743}
1744static inline u32 sim_control_recv_get__init_f(void)
1745{
1746 return 0x0U;
1747}
1748static inline u32 sim_control_recv_get_disabled_v(void)
1749{
1750 return 0x00000000U;
1751}
1752static inline u32 sim_control_recv_get_disabled_f(void)
1753{
1754 return 0x0U;
1755}
1756static inline u32 sim_control_recv_get_enabled_v(void)
1757{
1758 return 0x00000001U;
1759}
1760static inline u32 sim_control_recv_get_enabled_f(void)
1761{
1762 return 0x8U;
1763}
1764static inline u32 sim_control_event_put_s(void)
1765{
1766 return 1U;
1767}
1768static inline u32 sim_control_event_put_f(u32 v)
1769{
1770 return (v & 0x1U) << 4U;
1771}
1772static inline u32 sim_control_event_put_m(void)
1773{
1774 return 0x1U << 4U;
1775}
1776static inline u32 sim_control_event_put_v(u32 r)
1777{
1778 return (r >> 4U) & 0x1U;
1779}
1780static inline u32 sim_control_event_put__init_v(void)
1781{
1782 return 0x00000000U;
1783}
1784static inline u32 sim_control_event_put__init_f(void)
1785{
1786 return 0x0U;
1787}
1788static inline u32 sim_control_event_put_disabled_v(void)
1789{
1790 return 0x00000000U;
1791}
1792static inline u32 sim_control_event_put_disabled_f(void)
1793{
1794 return 0x0U;
1795}
1796static inline u32 sim_control_event_put_enabled_v(void)
1797{
1798 return 0x00000001U;
1799}
1800static inline u32 sim_control_event_put_enabled_f(void)
1801{
1802 return 0x10U;
1803}
1804static inline u32 sim_control_event_get_s(void)
1805{
1806 return 1U;
1807}
1808static inline u32 sim_control_event_get_f(u32 v)
1809{
1810 return (v & 0x1U) << 5U;
1811}
1812static inline u32 sim_control_event_get_m(void)
1813{
1814 return 0x1U << 5U;
1815}
1816static inline u32 sim_control_event_get_v(u32 r)
1817{
1818 return (r >> 5U) & 0x1U;
1819}
1820static inline u32 sim_control_event_get__init_v(void)
1821{
1822 return 0x00000000U;
1823}
1824static inline u32 sim_control_event_get__init_f(void)
1825{
1826 return 0x0U;
1827}
1828static inline u32 sim_control_event_get_disabled_v(void)
1829{
1830 return 0x00000000U;
1831}
1832static inline u32 sim_control_event_get_disabled_f(void)
1833{
1834 return 0x0U;
1835}
1836static inline u32 sim_control_event_get_enabled_v(void)
1837{
1838 return 0x00000001U;
1839}
1840static inline u32 sim_control_event_get_enabled_f(void)
1841{
1842 return 0x20U;
1843}
1844static inline u32 sim_dma_r(void)
1845{
1846 return 0x00000000U;
1847}
1848static inline u32 sim_dma_target_s(void)
1849{
1850 return 2U;
1851}
1852static inline u32 sim_dma_target_f(u32 v)
1853{
1854 return (v & 0x3U) << 0U;
1855}
1856static inline u32 sim_dma_target_m(void)
1857{
1858 return 0x3U << 0U;
1859}
1860static inline u32 sim_dma_target_v(u32 r)
1861{
1862 return (r >> 0U) & 0x3U;
1863}
1864static inline u32 sim_dma_target_phys_init_v(void)
1865{
1866 return 0x00000001U;
1867}
1868static inline u32 sim_dma_target_phys_init_f(void)
1869{
1870 return 0x1U;
1871}
1872static inline u32 sim_dma_target_phys__init_v(void)
1873{
1874 return 0x00000001U;
1875}
1876static inline u32 sim_dma_target_phys__init_f(void)
1877{
1878 return 0x1U;
1879}
1880static inline u32 sim_dma_target_phys__prod_v(void)
1881{
1882 return 0x00000001U;
1883}
1884static inline u32 sim_dma_target_phys__prod_f(void)
1885{
1886 return 0x1U;
1887}
1888static inline u32 sim_dma_target_phys_nvm_v(void)
1889{
1890 return 0x00000001U;
1891}
1892static inline u32 sim_dma_target_phys_nvm_f(void)
1893{
1894 return 0x1U;
1895}
1896static inline u32 sim_dma_target_phys_pci_v(void)
1897{
1898 return 0x00000002U;
1899}
1900static inline u32 sim_dma_target_phys_pci_f(void)
1901{
1902 return 0x2U;
1903}
1904static inline u32 sim_dma_target_phys_pci_coherent_v(void)
1905{
1906 return 0x00000003U;
1907}
1908static inline u32 sim_dma_target_phys_pci_coherent_f(void)
1909{
1910 return 0x3U;
1911}
1912static inline u32 sim_dma_status_s(void)
1913{
1914 return 1U;
1915}
1916static inline u32 sim_dma_status_f(u32 v)
1917{
1918 return (v & 0x1U) << 3U;
1919}
1920static inline u32 sim_dma_status_m(void)
1921{
1922 return 0x1U << 3U;
1923}
1924static inline u32 sim_dma_status_v(u32 r)
1925{
1926 return (r >> 3U) & 0x1U;
1927}
1928static inline u32 sim_dma_status_init_v(void)
1929{
1930 return 0x00000000U;
1931}
1932static inline u32 sim_dma_status_init_f(void)
1933{
1934 return 0x0U;
1935}
1936static inline u32 sim_dma_status__init_v(void)
1937{
1938 return 0x00000000U;
1939}
1940static inline u32 sim_dma_status__init_f(void)
1941{
1942 return 0x0U;
1943}
1944static inline u32 sim_dma_status__prod_v(void)
1945{
1946 return 0x00000000U;
1947}
1948static inline u32 sim_dma_status__prod_f(void)
1949{
1950 return 0x0U;
1951}
1952static inline u32 sim_dma_status_invalid_v(void)
1953{
1954 return 0x00000000U;
1955}
1956static inline u32 sim_dma_status_invalid_f(void)
1957{
1958 return 0x0U;
1959}
1960static inline u32 sim_dma_status_valid_v(void)
1961{
1962 return 0x00000001U;
1963}
1964static inline u32 sim_dma_status_valid_f(void)
1965{
1966 return 0x8U;
1967}
1968static inline u32 sim_dma_size_s(void)
1969{
1970 return 2U;
1971}
1972static inline u32 sim_dma_size_f(u32 v)
1973{
1974 return (v & 0x3U) << 4U;
1975}
1976static inline u32 sim_dma_size_m(void)
1977{
1978 return 0x3U << 4U;
1979}
1980static inline u32 sim_dma_size_v(u32 r)
1981{
1982 return (r >> 4U) & 0x3U;
1983}
1984static inline u32 sim_dma_size_init_v(void)
1985{
1986 return 0x00000000U;
1987}
1988static inline u32 sim_dma_size_init_f(void)
1989{
1990 return 0x0U;
1991}
1992static inline u32 sim_dma_size__init_v(void)
1993{
1994 return 0x00000000U;
1995}
1996static inline u32 sim_dma_size__init_f(void)
1997{
1998 return 0x0U;
1999}
2000static inline u32 sim_dma_size__prod_v(void)
2001{
2002 return 0x00000000U;
2003}
2004static inline u32 sim_dma_size__prod_f(void)
2005{
2006 return 0x0U;
2007}
2008static inline u32 sim_dma_size_4kb_v(void)
2009{
2010 return 0x00000000U;
2011}
2012static inline u32 sim_dma_size_4kb_f(void)
2013{
2014 return 0x0U;
2015}
2016static inline u32 sim_dma_size_8kb_v(void)
2017{
2018 return 0x00000001U;
2019}
2020static inline u32 sim_dma_size_8kb_f(void)
2021{
2022 return 0x10U;
2023}
2024static inline u32 sim_dma_size_12kb_v(void)
2025{
2026 return 0x00000002U;
2027}
2028static inline u32 sim_dma_size_12kb_f(void)
2029{
2030 return 0x20U;
2031}
2032static inline u32 sim_dma_size_16kb_v(void)
2033{
2034 return 0x00000003U;
2035}
2036static inline u32 sim_dma_size_16kb_f(void)
2037{
2038 return 0x30U;
2039}
2040static inline u32 sim_dma_addr_lo_s(void)
2041{
2042 return 20U;
2043}
2044static inline u32 sim_dma_addr_lo_f(u32 v)
2045{
2046 return (v & 0xfffffU) << 12U;
2047}
2048static inline u32 sim_dma_addr_lo_m(void)
2049{
2050 return 0xfffffU << 12U;
2051}
2052static inline u32 sim_dma_addr_lo_v(u32 r)
2053{
2054 return (r >> 12U) & 0xfffffU;
2055}
2056static inline u32 sim_dma_addr_lo__init_v(void)
2057{
2058 return 0x00000000U;
2059}
2060static inline u32 sim_dma_addr_lo__init_f(void)
2061{
2062 return 0x0U;
2063}
2064static inline u32 sim_dma_addr_lo__prod_v(void)
2065{
2066 return 0x00000000U;
2067}
2068static inline u32 sim_dma_addr_lo__prod_f(void)
2069{
2070 return 0x0U;
2071}
2072static inline u32 sim_dma_hi_r(void)
2073{
2074 return 0x00000004U;
2075}
2076static inline u32 sim_dma_hi_addr_s(void)
2077{
2078 return 20U;
2079}
2080static inline u32 sim_dma_hi_addr_f(u32 v)
2081{
2082 return (v & 0xfffffU) << 0U;
2083}
2084static inline u32 sim_dma_hi_addr_m(void)
2085{
2086 return 0xfffffU << 0U;
2087}
2088static inline u32 sim_dma_hi_addr_v(u32 r)
2089{
2090 return (r >> 0U) & 0xfffffU;
2091}
2092static inline u32 sim_dma_hi_addr__init_v(void)
2093{
2094 return 0x00000000U;
2095}
2096static inline u32 sim_dma_hi_addr__init_f(void)
2097{
2098 return 0x0U;
2099}
2100static inline u32 sim_dma_hi_addr__prod_v(void)
2101{
2102 return 0x00000000U;
2103}
2104static inline u32 sim_dma_hi_addr__prod_f(void)
2105{
2106 return 0x0U;
2107}
2108static inline u32 sim_msg_header_version_r(void)
2109{
2110 return 0x00000000U;
2111}
2112static inline u32 sim_msg_header_version_major_tot_v(void)
2113{
2114 return 0x03000000U;
2115}
2116static inline u32 sim_msg_header_version_minor_tot_v(void)
2117{
2118 return 0x00000000U;
2119}
2120static inline u32 sim_msg_signature_r(void)
2121{
2122 return 0x00000004U;
2123}
2124static inline u32 sim_msg_signature_valid_v(void)
2125{
2126 return 0x43505256U;
2127}
2128static inline u32 sim_msg_length_r(void)
2129{
2130 return 0x00000008U;
2131}
2132static inline u32 sim_msg_function_r(void)
2133{
2134 return 0x0000000cU;
2135}
2136static inline u32 sim_msg_function_sim_escape_read_v(void)
2137{
2138 return 0x00000023U;
2139}
2140static inline u32 sim_msg_function_sim_escape_write_v(void)
2141{
2142 return 0x00000024U;
2143}
2144static inline u32 sim_msg_result_r(void)
2145{
2146 return 0x00000010U;
2147}
2148static inline u32 sim_msg_result_success_v(void)
2149{
2150 return 0x00000000U;
2151}
2152static inline u32 sim_msg_result_rpc_pending_v(void)
2153{
2154 return 0xFFFFFFFFU;
2155}
2156static inline u32 sim_msg_sequence_r(void)
2157{
2158 return 0x00000018U;
2159}
2160static inline u32 sim_msg_spare_r(void)
2161{
2162 return 0x0000001cU;
2163}
2164static inline u32 sim_msg_spare__init_v(void)
2165{
2166 return 0x00000000U;
2167}
2168
2169#endif /* __hw_sim_pci_h__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-30 18:20:03 -0400