1 files changed, 6 insertions, 2 deletions

diff --git a/include/nvgpu/gk20a.h b/include/nvgpu/gk20a.h
index aa95969..19bfaee 100644
--- a/include/nvgpu/gk20a.h
+++ b/include/nvgpu/gk20a.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * GK20A Graphics
  *
@@ -517,6 +517,7 @@ struct gpu_ops {
                                         u32 *priv_addr_table,
                                         u32 *priv_addr_table_index);
                 u32 (*fecs_ctxsw_mailbox_size)(void);
+                u32 (*gpc0_gpccs_ctxsw_mailbox_size)(void);
                 int (*init_sw_bundle64)(struct gk20a *g);
                 int (*alloc_global_ctx_buffers)(struct gk20a *g);
                 int (*map_global_ctx_buffers)(struct gk20a *g,
@@ -719,7 +720,7 @@ struct gpu_ops {
                                 struct ch_state *ch_state);
                 u32 (*intr_0_error_mask)(struct gk20a *g);
                 int (*is_preempt_pending)(struct gk20a *g, u32 id,
-                        unsigned int id_type);
+                        unsigned int id_type, bool preempt_retries_left);
                 void (*init_pbdma_intr_descs)(struct fifo_gk20a *f);
                 int (*reset_enable_hw)(struct gk20a *g);
                 int (*setup_userd)(struct channel_gk20a *c);
@@ -1079,6 +1080,7 @@ struct gpu_ops {
                 u32 (*pmu_pg_supported_engines_list)(struct gk20a *g);
                 u32 (*pmu_pg_engines_feature_list)(struct gk20a *g,
                         u32 pg_engine_id);
+                int (*pmu_process_pg_event)(struct gk20a *g, void *pmumsg);
                 bool (*pmu_is_lpwr_feature_supported)(struct gk20a *g,
                         u32 feature_id);
                 int (*pmu_lpwr_enable_pg)(struct gk20a *g, bool pstate_lock);
@@ -1793,6 +1795,8 @@ bool gk20a_check_poweron(struct gk20a *g);
 int gk20a_prepare_poweroff(struct gk20a *g);
 int gk20a_finalize_poweron(struct gk20a *g);
 
+int nvgpu_wait_for_stall_interrupts(struct gk20a *g, u32 timeout);
+int nvgpu_wait_for_nonstall_interrupts(struct gk20a *g, u32 timeout);
 void nvgpu_wait_for_deferred_interrupts(struct gk20a *g);
 
 struct gk20a * __must_check gk20a_get(struct gk20a *g);