1 files changed, 1803 insertions, 0 deletions

diff --git a/include/nvgpu/gk20a.h b/include/nvgpu/gk20a.h
new file mode 100644
index 0000000..aa95969
--- /dev/null
+++ b/include/nvgpu/gk20a.h
@@ -0,0 +1,1803 @@
+/*
+ * Copyright (c) 2011-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * GK20A Graphics
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef GK20A_H
+#define GK20A_H
+
+struct gk20a;
+struct fifo_gk20a;
+struct channel_gk20a;
+struct gr_gk20a;
+struct sim_nvgpu;
+struct gk20a_ctxsw_ucode_segments;
+struct gk20a_fecs_trace;
+struct gk20a_ctxsw_trace;
+struct acr_desc;
+struct nvgpu_mem_alloc_tracker;
+struct dbg_profiler_object_data;
+struct gk20a_debug_output;
+struct nvgpu_clk_pll_debug_data;
+struct nvgpu_nvhost_dev;
+struct nvgpu_cpu_time_correlation_sample;
+struct nvgpu_mem_sgt;
+struct nvgpu_warpstate;
+struct nvgpu_clk_session;
+struct nvgpu_clk_arb;
+#ifdef CONFIG_GK20A_CTXSW_TRACE
+struct nvgpu_gpu_ctxsw_trace_filter;
+#endif
+struct priv_cmd_entry;
+struct nvgpu_setup_bind_args;
+
+#ifdef __KERNEL__
+#include <linux/notifier.h>
+#endif
+#include <nvgpu/lock.h>
+#include <nvgpu/thread.h>
+
+#include <nvgpu/mm.h>
+#include <nvgpu/as.h>
+#include <nvgpu/log.h>
+#include <nvgpu/pramin.h>
+#include <nvgpu/acr/nvgpu_acr.h>
+#include <nvgpu/kref.h>
+#include <nvgpu/falcon.h>
+#include <nvgpu/pmu.h>
+#include <nvgpu/atomic.h>
+#include <nvgpu/barrier.h>
+#include <nvgpu/rwsem.h>
+#include <nvgpu/nvlink.h>
+#include <nvgpu/sim.h>
+#include <nvgpu/ecc.h>
+#include <nvgpu/tsg.h>
+#include <nvgpu/sec2.h>
+#include <nvgpu/sched.h>
+
+#include "gk20a/clk_gk20a.h"
+#include "gk20a/ce2_gk20a.h"
+#include "gk20a/fifo_gk20a.h"
+#include "clk/clk.h"
+#include "pmu_perf/pmu_perf.h"
+#include "pmgr/pmgr.h"
+#include "therm/thrm.h"
+
+#ifdef CONFIG_DEBUG_FS
+struct railgate_stats {
+        unsigned long last_rail_gate_start;
+        unsigned long last_rail_gate_complete;
+        unsigned long last_rail_ungate_start;
+        unsigned long last_rail_ungate_complete;
+        unsigned long total_rail_gate_time_ms;
+        unsigned long total_rail_ungate_time_ms;
+        unsigned long railgating_cycle_count;
+};
+#endif
+
+enum gk20a_cbc_op {
+        gk20a_cbc_op_clear,
+        gk20a_cbc_op_clean,
+        gk20a_cbc_op_invalidate,
+};
+
+#define MC_INTR_UNIT_DISABLE    false
+#define MC_INTR_UNIT_ENABLE             true
+
+#define GPU_LIT_NUM_GPCS        0
+#define GPU_LIT_NUM_PES_PER_GPC 1
+#define GPU_LIT_NUM_ZCULL_BANKS 2
+#define GPU_LIT_NUM_TPC_PER_GPC 3
+#define GPU_LIT_NUM_SM_PER_TPC  4
+#define GPU_LIT_NUM_FBPS        5
+#define GPU_LIT_GPC_BASE        6
+#define GPU_LIT_GPC_STRIDE      7
+#define GPU_LIT_GPC_SHARED_BASE 8
+#define GPU_LIT_TPC_IN_GPC_BASE 9
+#define GPU_LIT_TPC_IN_GPC_STRIDE 10
+#define GPU_LIT_TPC_IN_GPC_SHARED_BASE 11
+#define GPU_LIT_PPC_IN_GPC_BASE 12
+#define GPU_LIT_PPC_IN_GPC_STRIDE 13
+#define GPU_LIT_PPC_IN_GPC_SHARED_BASE 14
+#define GPU_LIT_ROP_BASE        15
+#define GPU_LIT_ROP_STRIDE      16
+#define GPU_LIT_ROP_SHARED_BASE 17
+#define GPU_LIT_HOST_NUM_ENGINES 18
+#define GPU_LIT_HOST_NUM_PBDMA  19
+#define GPU_LIT_LTC_STRIDE      20
+#define GPU_LIT_LTS_STRIDE      21
+#define GPU_LIT_NUM_FBPAS       22
+#define GPU_LIT_FBPA_STRIDE     23
+#define GPU_LIT_FBPA_BASE       24
+#define GPU_LIT_FBPA_SHARED_BASE 25
+#define GPU_LIT_SM_PRI_STRIDE   26
+#define GPU_LIT_SMPC_PRI_BASE           27
+#define GPU_LIT_SMPC_PRI_SHARED_BASE    28
+#define GPU_LIT_SMPC_PRI_UNIQUE_BASE    29
+#define GPU_LIT_SMPC_PRI_STRIDE         30
+#define GPU_LIT_TWOD_CLASS      31
+#define GPU_LIT_THREED_CLASS    32
+#define GPU_LIT_COMPUTE_CLASS   33
+#define GPU_LIT_GPFIFO_CLASS    34
+#define GPU_LIT_I2M_CLASS       35
+#define GPU_LIT_DMA_COPY_CLASS  36
+#define GPU_LIT_GPC_PRIV_STRIDE 37
+#define GPU_LIT_PERFMON_PMMGPCTPCA_DOMAIN_START 38
+#define GPU_LIT_PERFMON_PMMGPCTPCB_DOMAIN_START 39
+#define GPU_LIT_PERFMON_PMMGPCTPC_DOMAIN_COUNT  40
+#define GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_START 41
+#define GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_COUNT 42
+#define GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_START 43
+#define GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_COUNT 44
+
+#define nvgpu_get_litter_value(g, v) (g)->ops.get_litter_value((g), v)
+
+#define MAX_TPC_PG_CONFIGS      9
+
+enum nvgpu_unit;
+
+enum nvgpu_flush_op;
+enum gk20a_mem_rw_flag;
+
+struct _resmgr_context;
+struct nvgpu_gpfifo_entry;
+
+struct nvgpu_gpfifo_userdata {
+        struct nvgpu_gpfifo_entry __user *entries;
+        struct _resmgr_context *context;
+};
+
+/*
+ * gpu_ops should only contain function pointers! Non-function pointer members
+ * should go in struct gk20a or be implemented with the boolean flag API defined
+ * in nvgpu/enabled.h
+ */
+
+/* index for FB fault buffer functions */
+#define NVGPU_FB_MMU_FAULT_NONREPLAY_REG_INDEX          0U
+#define NVGPU_FB_MMU_FAULT_REPLAY_REG_INDEX             1U
+#define NVGPU_FB_MMU_FAULT_BUF_DISABLED                 0U
+#define NVGPU_FB_MMU_FAULT_BUF_ENABLED                  1U
+
+/* Parameters for init_elcg_mode/init_blcg_mode */
+enum {
+        ELCG_RUN,       /* clk always run, i.e. disable elcg */
+        ELCG_STOP,      /* clk is stopped */
+        ELCG_AUTO       /* clk will run when non-idle, standard elcg mode */
+};
+
+enum {
+        BLCG_RUN,       /* clk always run, i.e. disable blcg */
+        BLCG_AUTO       /* clk will run when non-idle, standard blcg mode */
+};
+
+struct gpu_ops {
+        struct {
+                int (*determine_L2_size_bytes)(struct gk20a *gk20a);
+                u64 (*get_cbc_base_divisor)(struct gk20a *g);
+                int (*init_comptags)(struct gk20a *g, struct gr_gk20a *gr);
+                int (*cbc_ctrl)(struct gk20a *g, enum gk20a_cbc_op op,
+                                u32 min, u32 max);
+                void (*set_zbc_color_entry)(struct gk20a *g,
+                                            struct zbc_entry *color_val,
+                                            u32 index);
+                void (*set_zbc_depth_entry)(struct gk20a *g,
+                                            struct zbc_entry *depth_val,
+                                            u32 index);
+                void (*set_zbc_s_entry)(struct gk20a *g,
+                                            struct zbc_entry *s_val,
+                                            u32 index);
+                void (*init_cbc)(struct gk20a *g, struct gr_gk20a *gr);
+                void (*set_enabled)(struct gk20a *g, bool enabled);
+                void (*init_fs_state)(struct gk20a *g);
+                void (*isr)(struct gk20a *g);
+                u32 (*cbc_fix_config)(struct gk20a *g, int base);
+                void (*flush)(struct gk20a *g);
+                void (*intr_en_illegal_compstat)(struct gk20a *g, bool enable);
+                bool (*pri_is_ltc_addr)(struct gk20a *g, u32 addr);
+                bool (*is_ltcs_ltss_addr)(struct gk20a *g, u32 addr);
+                bool (*is_ltcn_ltss_addr)(struct gk20a *g, u32 addr);
+                void (*split_lts_broadcast_addr)(struct gk20a *g, u32 addr,
+                                                        u32 *priv_addr_table,
+                                                        u32 *priv_addr_table_index);
+                void (*split_ltc_broadcast_addr)(struct gk20a *g, u32 addr,
+                                                        u32 *priv_addr_table,
+                                                        u32 *priv_addr_table_index);
+        } ltc;
+        struct {
+                void (*isr_stall)(struct gk20a *g, u32 inst_id, u32 pri_base);