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1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef NVGPU_FALCON_H
24#define NVGPU_FALCON_H
25
26#include <nvgpu/types.h>
27#include <nvgpu/lock.h>
28
29/*
30 * Falcon Id Defines
31 */
32#define FALCON_ID_PMU (0U)
33#define FALCON_ID_GSPLITE (1U)
34#define FALCON_ID_FECS (2U)
35#define FALCON_ID_GPCCS (3U)
36#define FALCON_ID_NVDEC (4U)
37#define FALCON_ID_SEC2 (7U)
38#define FALCON_ID_MINION (10U)
39
40/*
41 * Falcon Base address Defines
42 */
43#define FALCON_NVDEC_BASE 0x00084000
44#define FALCON_PWR_BASE 0x0010a000
45#define FALCON_SEC_BASE 0x00087000
46#define FALCON_FECS_BASE 0x00409000
47#define FALCON_GPCCS_BASE 0x0041a000
48
49/* Falcon Register index */
50#define FALCON_REG_R0 (0)
51#define FALCON_REG_R1 (1)
52#define FALCON_REG_R2 (2)
53#define FALCON_REG_R3 (3)
54#define FALCON_REG_R4 (4)
55#define FALCON_REG_R5 (5)
56#define FALCON_REG_R6 (6)
57#define FALCON_REG_R7 (7)
58#define FALCON_REG_R8 (8)
59#define FALCON_REG_R9 (9)
60#define FALCON_REG_R10 (10)
61#define FALCON_REG_R11 (11)
62#define FALCON_REG_R12 (12)
63#define FALCON_REG_R13 (13)
64#define FALCON_REG_R14 (14)
65#define FALCON_REG_R15 (15)
66#define FALCON_REG_IV0 (16)
67#define FALCON_REG_IV1 (17)
68#define FALCON_REG_UNDEFINED (18)
69#define FALCON_REG_EV (19)
70#define FALCON_REG_SP (20)
71#define FALCON_REG_PC (21)
72#define FALCON_REG_IMB (22)
73#define FALCON_REG_DMB (23)
74#define FALCON_REG_CSW (24)
75#define FALCON_REG_CCR (25)
76#define FALCON_REG_SEC (26)
77#define FALCON_REG_CTX (27)
78#define FALCON_REG_EXCI (28)
79#define FALCON_REG_RSVD0 (29)
80#define FALCON_REG_RSVD1 (30)
81#define FALCON_REG_RSVD2 (31)
82#define FALCON_REG_SIZE (32)
83
84#define FALCON_MAILBOX_0 0x0
85#define FALCON_MAILBOX_1 0x1
86#define FALCON_MAILBOX_COUNT 0x02
87#define FALCON_BLOCK_SIZE 0x100U
88
89#define GET_IMEM_TAG(IMEM_ADDR) (IMEM_ADDR >> 8)
90
91#define GET_NEXT_BLOCK(ADDR) \
92 ((((ADDR + (FALCON_BLOCK_SIZE - 1)) & ~(FALCON_BLOCK_SIZE-1)) \
93 / FALCON_BLOCK_SIZE) << 8)
94
95/*
96 * Falcon HWCFG request read types defines
97 */
98enum flcn_hwcfg_read {
99 FALCON_IMEM_SIZE = 0,
100 FALCON_DMEM_SIZE,
101 FALCON_CORE_REV,
102 FALCON_SECURITY_MODEL,
103 FLACON_MAILBOX_COUNT
104};
105
106/*
107 * Falcon HWCFG request write types defines
108 */
109enum flcn_hwcfg_write {
110 FALCON_STARTCPU = 0,
111 FALCON_STARTCPU_SECURE,
112 FALCON_BOOTVEC,
113 FALCON_ITF_EN
114};
115
116#define FALCON_MEM_SCRUBBING_TIMEOUT_MAX 1000
117#define FALCON_MEM_SCRUBBING_TIMEOUT_DEFAULT 10
118
119enum flcn_dma_dir {
120 DMA_TO_FB = 0,
121 DMA_FROM_FB
122};
123
124enum flcn_mem_type {
125 MEM_DMEM = 0,
126 MEM_IMEM
127};
128
129/* Falcon ucode header format
130 * OS Code Offset
131 * OS Code Size
132 * OS Data Offset
133 * OS Data Size
134 * NumApps (N)
135 * App 0 Code Offset
136 * App 0 Code Size
137 * . . . .
138 * App N - 1 Code Offset
139 * App N - 1 Code Size
140 * App 0 Data Offset
141 * App 0 Data Size
142 * . . . .
143 * App N - 1 Data Offset
144 * App N - 1 Data Size
145 * OS Ovl Offset
146 * OS Ovl Size
147*/
148#define OS_CODE_OFFSET 0x0
149#define OS_CODE_SIZE 0x1
150#define OS_DATA_OFFSET 0x2
151#define OS_DATA_SIZE 0x3
152#define NUM_APPS 0x4
153#define APP_0_CODE_OFFSET 0x5
154#define APP_0_CODE_SIZE 0x6
155
156struct nvgpu_falcon_dma_info {
157 u32 fb_base;
158 u32 fb_off;
159 u32 flcn_mem_off;
160 u32 size_in_bytes;
161 enum flcn_dma_dir dir;
162 u32 ctx_dma;
163 enum flcn_mem_type flcn_mem;
164 u32 is_wait_complete;
165};
166
167struct gk20a;
168struct nvgpu_falcon;
169struct nvgpu_falcon_bl_info;
170
171/* Queue Type */
172#define QUEUE_TYPE_DMEM 0x0U
173#define QUEUE_TYPE_EMEM 0x1U
174
175struct nvgpu_falcon_queue {
176
177 /* Queue Type (queue_type) */
178 u8 queue_type;
179
180 /* used by nvgpu, for command LPQ/HPQ */
181 struct nvgpu_mutex mutex;
182
183 /* current write position */
184 u32 position;
185 /* physical dmem offset where this queue begins */
186 u32 offset;
187 /* logical queue identifier */
188 u32 id;
189 /* physical queue index */
190 u32 index;
191 /* in bytes */
192 u32 size;
193 /* open-flag */
194 u32 oflag;
195
196 /* queue type(DMEM-Q/FB-Q) specific ops */
197 int (*rewind)(struct nvgpu_falcon *flcn,
198 struct nvgpu_falcon_queue *queue);
199 int (*pop)(struct nvgpu_falcon *flcn,
200 struct nvgpu_falcon_queue *queue, void *data, u32 size,
201 u32 *bytes_read);
202 int (*push)(struct nvgpu_falcon *flcn,
203 struct nvgpu_falcon_queue *queue, void *data, u32 size);
204 bool (*has_room)(struct nvgpu_falcon *flcn,
205 struct nvgpu_falcon_queue *queue, u32 size,
206 bool *need_rewind);
207 int (*tail)(struct nvgpu_falcon *flcn,
208 struct nvgpu_falcon_queue *queue, u32 *tail, bool set);
209 int (*head)(struct nvgpu_falcon *flcn,
210 struct nvgpu_falcon_queue *queue, u32 *head, bool set);
211};
212
213struct nvgpu_falcon_version_ops {
214 void (*start_cpu_secure)(struct nvgpu_falcon *flcn);
215 void (*write_dmatrfbase)(struct nvgpu_falcon *flcn, u32 addr);
216};
217
218/* ops which are falcon engine specific */
219struct nvgpu_falcon_engine_dependency_ops {
220 int (*reset_eng)(struct gk20a *g);
221 int (*queue_head)(struct gk20a *g, struct nvgpu_falcon_queue *queue,
222 u32 *head, bool set);
223 int (*queue_tail)(struct gk20a *g, struct nvgpu_falcon_queue *queue,
224 u32 *tail, bool set);
225 void (*msgq_tail)(struct gk20a *g, u32 *tail, bool set);
226 int (*copy_from_emem)(struct nvgpu_falcon *flcn, u32 src, u8 *dst,
227 u32 size, u8 port);
228 int (*copy_to_emem)(struct nvgpu_falcon *flcn, u32 dst, u8 *src,
229 u32 size, u8 port);
230};
231
232struct nvgpu_falcon_ops {
233 int (*reset)(struct nvgpu_falcon *flcn);
234 void (*set_irq)(struct nvgpu_falcon *flcn, bool enable);
235 bool (*clear_halt_interrupt_status)(struct nvgpu_falcon *flcn);
236 bool (*is_falcon_cpu_halted)(struct nvgpu_falcon *flcn);
237 bool (*is_falcon_idle)(struct nvgpu_falcon *flcn);
238 bool (*is_falcon_scrubbing_done)(struct nvgpu_falcon *flcn);
239 int (*copy_from_dmem)(struct nvgpu_falcon *flcn, u32 src, u8 *dst,
240 u32 size, u8 port);
241 int (*copy_to_dmem)(struct nvgpu_falcon *flcn, u32 dst, u8 *src,
242 u32 size, u8 port);
243 int (*copy_from_imem)(struct nvgpu_falcon *flcn, u32 src, u8 *dst,
244 u32 size, u8 port);
245 int (*copy_to_imem)(struct nvgpu_falcon *flcn, u32 dst, u8 *src,
246 u32 size, u8 port, bool sec, u32 tag);
247 int (*dma_copy)(struct nvgpu_falcon *flcn,
248 struct nvgpu_falcon_dma_info *dma_info);
249 u32 (*mailbox_read)(struct nvgpu_falcon *flcn, u32 mailbox_index);
250 void (*mailbox_write)(struct nvgpu_falcon *flcn, u32 mailbox_index,
251 u32 data);
252 int (*bootstrap)(struct nvgpu_falcon *flcn, u32 boot_vector);
253 void (*dump_falcon_stats)(struct nvgpu_falcon *flcn);
254 int (*bl_bootstrap)(struct nvgpu_falcon *flcn,
255 struct nvgpu_falcon_bl_info *bl_info);
256};
257
258struct nvgpu_falcon_bl_info {
259 void *bl_src;
260 u8 *bl_desc;
261 u32 bl_desc_size;
262 u32 bl_size;
263 u32 bl_start_tag;
264};
265
266struct nvgpu_falcon {
267 struct gk20a *g;
268 u32 flcn_id;
269 u32 flcn_base;
270 u32 flcn_core_rev;
271 bool is_falcon_supported;
272 bool is_interrupt_enabled;
273 u32 intr_mask;
274 u32 intr_dest;
275 bool isr_enabled;
276 struct nvgpu_mutex isr_mutex;
277 struct nvgpu_mutex copy_lock;
278 struct nvgpu_falcon_ops flcn_ops;
279 struct nvgpu_falcon_version_ops flcn_vops;
280 struct nvgpu_falcon_engine_dependency_ops flcn_engine_dep_ops;
281};
282
283int nvgpu_flcn_wait_idle(struct nvgpu_falcon *flcn);
284int nvgpu_flcn_wait_for_halt(struct nvgpu_falcon *flcn, unsigned int timeout);
285int nvgpu_flcn_clear_halt_intr_status(struct nvgpu_falcon *flcn,
286 unsigned int timeout);
287int nvgpu_flcn_reset(struct nvgpu_falcon *flcn);
288void nvgpu_flcn_set_irq(struct nvgpu_falcon *flcn, bool enable,
289 u32 intr_mask, u32 intr_dest);
290bool nvgpu_flcn_get_mem_scrubbing_status(struct nvgpu_falcon *flcn);
291int nvgpu_flcn_mem_scrub_wait(struct nvgpu_falcon *flcn);
292bool nvgpu_flcn_get_cpu_halted_status(struct nvgpu_falcon *flcn);
293bool nvgpu_flcn_get_idle_status(struct nvgpu_falcon *flcn);
294int nvgpu_flcn_copy_from_emem(struct nvgpu_falcon *flcn,
295 u32 src, u8 *dst, u32 size, u8 port);
296int nvgpu_flcn_copy_to_emem(struct nvgpu_falcon *flcn,
297 u32 dst, u8 *src, u32 size, u8 port);
298int nvgpu_flcn_copy_from_dmem(struct nvgpu_falcon *flcn,
299 u32 src, u8 *dst, u32 size, u8 port);
300int nvgpu_flcn_copy_to_dmem(struct nvgpu_falcon *flcn,
301 u32 dst, u8 *src, u32 size, u8 port);
302int nvgpu_flcn_copy_to_imem(struct nvgpu_falcon *flcn,
303 u32 dst, u8 *src, u32 size, u8 port, bool sec, u32 tag);
304int nvgpu_flcn_copy_from_imem(struct nvgpu_falcon *flcn,
305 u32 src, u8 *dst, u32 size, u8 port);
306int nvgpu_flcn_dma_copy(struct nvgpu_falcon *flcn,
307 struct nvgpu_falcon_dma_info *dma_info);
308u32 nvgpu_flcn_mailbox_read(struct nvgpu_falcon *flcn, u32 mailbox_index);
309void nvgpu_flcn_mailbox_write(struct nvgpu_falcon *flcn, u32 mailbox_index,
310 u32 data);
311int nvgpu_flcn_bootstrap(struct nvgpu_falcon *flcn, u32 boot_vector);
312void nvgpu_flcn_print_dmem(struct nvgpu_falcon *flcn, u32 src, u32 size);
313void nvgpu_flcn_print_imem(struct nvgpu_falcon *flcn, u32 src, u32 size);
314void nvgpu_flcn_dump_stats(struct nvgpu_falcon *flcn);
315int nvgpu_flcn_bl_bootstrap(struct nvgpu_falcon *flcn,
316 struct nvgpu_falcon_bl_info *bl_info);
317
318/* queue public functions */
319int nvgpu_flcn_queue_init(struct nvgpu_falcon *flcn,
320 struct nvgpu_falcon_queue *queue);
321bool nvgpu_flcn_queue_is_empty(struct nvgpu_falcon *flcn,
322 struct nvgpu_falcon_queue *queue);
323int nvgpu_flcn_queue_rewind(struct nvgpu_falcon *flcn,
324 struct nvgpu_falcon_queue *queue);
325int nvgpu_flcn_queue_pop(struct nvgpu_falcon *flcn,
326 struct nvgpu_falcon_queue *queue, void *data, u32 size,
327 u32 *bytes_read);
328int nvgpu_flcn_queue_push(struct nvgpu_falcon *flcn,
329 struct nvgpu_falcon_queue *queue, void *data, u32 size);
330void nvgpu_flcn_queue_free(struct nvgpu_falcon *flcn,
331 struct nvgpu_falcon_queue *queue);
332
333int nvgpu_flcn_sw_init(struct gk20a *g, u32 flcn_id);
334
335#endif /* NVGPU_FALCON_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-30 22:22:10 -0400