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1/*
2 * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef NVGPU_CHANNEL_H
24#define NVGPU_CHANNEL_H
25
26#include <nvgpu/list.h>
27#include <nvgpu/lock.h>
28#include <nvgpu/timers.h>
29#include <nvgpu/cond.h>
30#include <nvgpu/atomic.h>
31#include <nvgpu/nvgpu_mem.h>
32#include <nvgpu/allocator.h>
33
34struct gk20a;
35struct dbg_session_gk20a;
36struct gk20a_fence;
37struct fifo_profile_gk20a;
38struct nvgpu_channel_sync;
39struct nvgpu_gpfifo_userdata;
40
41/* Flags to be passed to nvgpu_channel_setup_bind() */
42#define NVGPU_SETUP_BIND_FLAGS_SUPPORT_VPR (1U << 0U)
43#define NVGPU_SETUP_BIND_FLAGS_SUPPORT_DETERMINISTIC (1U << 1U)
44#define NVGPU_SETUP_BIND_FLAGS_REPLAYABLE_FAULTS_ENABLE (1U << 2U)
45#define NVGPU_SETUP_BIND_FLAGS_USERMODE_SUPPORT (1U << 3U)
46
47/* Flags to be passed to nvgpu_submit_channel_gpfifo() */
48#define NVGPU_SUBMIT_FLAGS_FENCE_WAIT (1U << 0U)
49#define NVGPU_SUBMIT_FLAGS_FENCE_GET (1U << 1U)
50#define NVGPU_SUBMIT_FLAGS_HW_FORMAT (1U << 2U)
51#define NVGPU_SUBMIT_FLAGS_SYNC_FENCE (1U << 3U)
52#define NVGPU_SUBMIT_FLAGS_SUPPRESS_WFI (1U << 4U)
53#define NVGPU_SUBMIT_FLAGS_SKIP_BUFFER_REFCOUNTING (1U << 5U)
54
55/*
56 * The binary format of 'struct nvgpu_channel_fence' introduced here
57 * should match that of 'struct nvgpu_fence' defined in uapi header, since
58 * this struct is intended to be a mirror copy of the uapi struct. This is
59 * not a hard requirement though because of nvgpu_get_fence_args conversion
60 * function.
61 */
62struct nvgpu_channel_fence {
63 u32 id;
64 u32 value;
65};
66
67/*
68 * The binary format of 'struct nvgpu_gpfifo_entry' introduced here
69 * should match that of 'struct nvgpu_gpfifo' defined in uapi header, since
70 * this struct is intended to be a mirror copy of the uapi struct. This is
71 * a rigid requirement because there's no conversion function and there are
72 * memcpy's present between the user gpfifo (of type nvgpu_gpfifo) and the
73 * kern gpfifo (of type nvgpu_gpfifo_entry).
74 */
75struct nvgpu_gpfifo_entry {
76 u32 entry0;
77 u32 entry1;
78};
79
80struct gpfifo_desc {
81 struct nvgpu_mem mem;
82 u32 entry_num;
83
84 u32 get;
85 u32 put;
86
87 bool wrap;
88
89 /* if gpfifo lives in vidmem or is forced to go via PRAMIN, first copy
90 * from userspace to pipe and then from pipe to gpu buffer */
91 void *pipe;
92};
93
94struct nvgpu_setup_bind_args {
95 u32 num_gpfifo_entries;
96 u32 num_inflight_jobs;
97 u32 userd_dmabuf_fd;
98 u64 userd_dmabuf_offset;
99 u32 gpfifo_dmabuf_fd;
100 u64 gpfifo_dmabuf_offset;
101 u32 work_submit_token;
102 u32 flags;
103};
104
105struct notification {
106 struct {
107 u32 nanoseconds[2];
108 } timestamp;
109 u32 info32;
110 u16 info16;
111 u16 status;
112};
113
114struct priv_cmd_queue {
115 struct nvgpu_mem mem;
116 u32 size; /* num of entries in words */
117 u32 put; /* put for priv cmd queue */
118 u32 get; /* get for priv cmd queue */
119};
120
121struct priv_cmd_entry {
122 bool valid;
123 struct nvgpu_mem *mem;
124 u32 off; /* offset in mem, in u32 entries */
125 u64 gva;
126 u32 get; /* start of entry in queue */
127 u32 size; /* in words */
128};
129
130struct channel_gk20a_job {
131 struct nvgpu_mapped_buf **mapped_buffers;
132 int num_mapped_buffers;
133 struct gk20a_fence *post_fence;
134 struct priv_cmd_entry *wait_cmd;
135 struct priv_cmd_entry *incr_cmd;
136 struct nvgpu_list_node list;
137};
138
139static inline struct channel_gk20a_job *
140channel_gk20a_job_from_list(struct nvgpu_list_node *node)
141{
142 return (struct channel_gk20a_job *)
143 ((uintptr_t)node - offsetof(struct channel_gk20a_job, list));
144};
145
146struct channel_gk20a_joblist {
147 struct {
148 bool enabled;
149 unsigned int length;
150 unsigned int put;
151 unsigned int get;
152 struct channel_gk20a_job *jobs;
153 struct nvgpu_mutex read_lock;
154 } pre_alloc;
155
156 struct {
157 struct nvgpu_list_node jobs;
158 struct nvgpu_spinlock lock;
159 } dynamic;
160
161 /*
162 * Synchronize abort cleanup (when closing a channel) and job cleanup
163 * (asynchronously from worker) - protect from concurrent access when
164 * job resources are being freed.
165 */
166 struct nvgpu_mutex cleanup_lock;
167};
168
169struct channel_gk20a_timeout {
170 /* lock protects the running timer state */
171 struct nvgpu_spinlock lock;
172 struct nvgpu_timeout timer;
173 bool running;
174 u32 gp_get;
175 u64 pb_get;
176
177 /* lock not needed */
178 u32 limit_ms;
179 bool enabled;
180 bool debug_dump;
181};
182
183/*
184 * Track refcount actions, saving their stack traces. This number specifies how
185 * many most recent actions are stored in a buffer. Set to 0 to disable. 128
186 * should be enough to track moderately hard problems from the start.
187 */
188#define GK20A_CHANNEL_REFCOUNT_TRACKING 0
189/* Stack depth for the saved actions. */
190#define GK20A_CHANNEL_REFCOUNT_TRACKING_STACKLEN 8
191
192/*
193 * Because the puts and gets are not linked together explicitly (although they
194 * should always come in pairs), it's not possible to tell which ref holder to
195 * delete from the list when doing a put. So, just store some number of most
196 * recent gets and puts in a ring buffer, to obtain a history.
197 *
198 * These are zeroed when a channel is closed, so a new one starts fresh.
199 */
200
201enum channel_gk20a_ref_action_type {
202 channel_gk20a_ref_action_get,
203 channel_gk20a_ref_action_put
204};
205
206#if GK20A_CHANNEL_REFCOUNT_TRACKING
207
208#include <linux/stacktrace.h>
209
210struct channel_gk20a_ref_action {
211 enum channel_gk20a_ref_action_type type;
212 s64 timestamp_ms;
213 /*
214 * Many of these traces will be similar. Simpler to just capture
215 * duplicates than to have a separate database for the entries.
216 */
217 struct stack_trace trace;
218 unsigned long trace_entries[GK20A_CHANNEL_REFCOUNT_TRACKING_STACKLEN];
219};
220#endif
221
222/* this is the priv element of struct nvhost_channel */
223struct channel_gk20a {
224 struct gk20a *g; /* set only when channel is active */
225