1 files changed, 1123 insertions, 0 deletions

diff --git a/include/nvgpu/bios.h b/include/nvgpu/bios.h
new file mode 100644
index 0000000..7d729b6
--- /dev/null
+++ b/include/nvgpu/bios.h
@@ -0,0 +1,1123 @@
+/*
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_BIOS_H
+#define NVGPU_BIOS_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+#define PERF_PTRS_WIDTH 0x4
+#define PERF_PTRS_WIDTH_16 0x2
+
+enum {
+        CLOCKS_TABLE = 2,
+        CLOCK_PROGRAMMING_TABLE,
+        FLL_TABLE,
+        VIN_TABLE,
+        FREQUENCY_CONTROLLER_TABLE
+};
+
+enum {
+        PERFORMANCE_TABLE = 0,
+        MEMORY_CLOCK_TABLE,
+        MEMORY_TWEAK_TABLE,
+        POWER_CONTROL_TABLE,
+        THERMAL_CONTROL_TABLE,
+        THERMAL_DEVICE_TABLE,
+        THERMAL_COOLERS_TABLE,
+        PERFORMANCE_SETTINGS_SCRIPT,
+        CONTINUOUS_VIRTUAL_BINNING_TABLE,
+        POWER_SENSORS_TABLE = 0xA,
+        POWER_CAPPING_TABLE = 0xB,
+        POWER_TOPOLOGY_TABLE = 0xF,
+        THERMAL_CHANNEL_TABLE = 0x12,
+        VOLTAGE_RAIL_TABLE = 26,
+        VOLTAGE_DEVICE_TABLE,
+        VOLTAGE_POLICY_TABLE,
+        LOWPOWER_TABLE,
+        LOWPOWER_GR_TABLE = 32,
+        LOWPOWER_MS_TABLE = 33,
+};
+
+enum {
+        VP_FIELD_TABLE = 0,
+        VP_FIELD_REGISTER,
+        VP_TRANSLATION_TABLE,
+};
+
+struct bit_token {
+        u8 token_id;
+        u8 data_version;
+        u16 data_size;
+        u16 data_ptr;
+} __packed;
+
+#define BIOS_GET_FIELD(value, name) ((value & name##_MASK) >> name##_SHIFT)
+
+struct fll_descriptor_header {
+        u8 version;
+        u8 size;
+} __packed;
+
+#define FLL_DESCRIPTOR_HEADER_10_SIZE_4     4U
+#define FLL_DESCRIPTOR_HEADER_10_SIZE_6     6U
+
+struct fll_descriptor_header_10 {
+        u8 version;
+        u8 header_size;
+        u8 entry_size;
+        u8 entry_count;
+        u16 max_min_freq_mhz;
+} __packed;
+
+#define FLL_DESCRIPTOR_ENTRY_10_SIZE     15U
+
+struct fll_descriptor_entry_10 {
+        u8 fll_device_type;
+        u8 clk_domain;
+        u8 fll_device_id;
+        u16 lut_params;
+        u8 vin_idx_logic;
+        u8 vin_idx_sram;
+        u16 fll_params;
+        u8 min_freq_vfe_idx;
+        u8 freq_ctrl_idx;
+        u16 ref_freq_mhz;
+        u16 ffr_cutoff_freq_mhz;
+} __packed;
+
+#define NV_FLL_DESC_FLL_PARAMS_MDIV_MASK 0x1F
+#define NV_FLL_DESC_FLL_PARAMS_MDIV_SHIFT 0
+
+#define NV_FLL_DESC_FLL_PARAMS_SKIP_PLDIV_BELOW_DVCO_MIN_MASK 0x20
+#define NV_FLL_DESC_FLL_PARAMS_SKIP_PLDIV_BELOW_DVCO_MIN_SHIFT 5
+
+#define NV_FLL_DESC_LUT_PARAMS_VSELECT_MASK 0x3
+#define NV_FLL_DESC_LUT_PARAMS_VSELECT_SHIFT 0
+
+#define NV_FLL_DESC_LUT_PARAMS_HYSTERISIS_THRESHOLD_MASK 0x3C
+#define NV_FLL_DESC_LUT_PARAMS_HYSTERISIS_THRESHOLD_SHIFT 2
+
+struct vin_descriptor_header_10 {
+        u8 version;
+        u8 header_sizee;
+        u8 entry_size;
+        u8 entry_count;
+        u8 flags0;
+        u32 vin_cal;
+} __packed;
+
+struct vin_descriptor_entry_10 {
+        u8 vin_device_type;
+        u8 volt_domain_vbios;
+        u8 vin_device_id;
+} __packed;
+
+#define NV_VIN_DESC_FLAGS0_VIN_CAL_REVISION_MASK 0x7
+#define NV_VIN_DESC_FLAGS0_VIN_CAL_REVISION_SHIFT 0
+
+#define NV_VIN_DESC_FLAGS0_VIN_CAL_TYPE_MASK 0xF0
+#define NV_VIN_DESC_FLAGS0_VIN_CAL_TYPE_SHIFT 4
+
+#define NV_VIN_DESC_FLAGS0_DISABLE_CONTROL_MASK 0x8
+#define NV_VIN_DESC_FLAGS0_DISABLE_CONTROL_SHIFT 3
+
+#define NV_VIN_DESC_VIN_CAL_SLOPE_FRACTION_MASK 0x1FF
+#define NV_VIN_DESC_VIN_CAL_SLOPE_FRACTION_SHIFT 0
+
+#define NV_VIN_DESC_VIN_CAL_SLOPE_INTEGER_MASK 0x3C00
+#define NV_VIN_DESC_VIN_CAL_SLOPE_INTEGER_SHIFT  10
+
+#define NV_VIN_DESC_VIN_CAL_INTERCEPT_FRACTION_MASK 0x3C000
+#define NV_VIN_DESC_VIN_CAL_INTERCEPT_FRACTION_SHIFT 14
+
+#define NV_VIN_DESC_VIN_CAL_INTERCEPT_INTEGER_MASK 0xFFC0000
+#define NV_VIN_DESC_VIN_CAL_INTERCEPT_INTEGER_SHIFT 18
+
+#define NV_VIN_DESC_VIN_CAL_OFFSET_MASK 0x7F
+#define NV_VIN_DESC_VIN_CAL_OFFSET_SHIFT 0
+
+#define NV_VIN_DESC_VIN_CAL_GAIN_MASK 0xF80
+#define NV_VIN_DESC_VIN_CAL_GAIN_SHIFT 7
+
+#define VBIOS_CLOCKS_TABLE_1X_HEADER_SIZE_07 0x07U
+struct vbios_clocks_table_1x_header {
+        u8 version;
+        u8 header_size;
+        u8 entry_size;
+        u8 entry_count;
+        u8 clocks_hal;
+        u16 cntr_sampling_periodms;
+} __packed;
+
+#define VBIOS_CLOCKS_TABLE_35_HEADER_SIZE_09 0x09U
+struct vbios_clocks_table_35_header {
+        u8 version;
+        u8 header_size;
+        u8 entry_size;
+        u8 entry_count;
+        u8 clocks_hal;
+        u16 cntr_sampling_periodms;
+        u16 reference_window;
+} __packed;
+
+#define VBIOS_CLOCKS_TABLE_1X_ENTRY_SIZE_09                                0x09U
+struct vbios_clocks_table_1x_entry {
+        u8 flags0;
+        u16 param0;
+        u32 param1;
+        u16 param2;
+} __packed;
+
+#define VBIOS_CLOCKS_TABLE_35_ENTRY_SIZE_11                                0x0BU
+struct vbios_clocks_table_35_entry {
+        u8 flags0;
+        u16 param0;
+        u32 param1;
+        u16 param2;
+        u16 param3;
+} __packed;
+
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_MASK                    0x1F
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_SHIFT                   0
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_FIXED                   0x00
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_MASTER                  0x01
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_SLAVE                   0x02
+
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_FIRST_MASK  0xFF
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_FIRST_SHIFT  0
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_LAST_MASK  0xFF00
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_LAST_SHIFT 0x08
+
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_FIXED_FREQUENCY_MHZ_MASK        0xFFFF
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_FIXED_FREQUENCY_MHZ_SHIFT       0
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MIN_MHZ_MASK 0xFFFF
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MIN_MHZ_SHIFT 0
+
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MAX_MHZ_MASK 0xFFFF0000
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MAX_MHZ_SHIFT 0
+
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_SLAVE_MASTER_DOMAIN_MASK         0xF
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_SLAVE_MASTER_DOMAIN_SHIFT       0
+
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX_MASK 0xF
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX_SHIFT 0
+
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_AWARE_ORDERING_IDX_MASK     0xF0
+#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_AWARE_ORDERING_IDX_SHIFT   4