1 files changed, 0 insertions, 144 deletions
diff --git a/include/nvgpu/acr/acr_flcnbl.h b/include/nvgpu/acr/acr_flcnbl.h
deleted file mode 100644
index ad697b2..0000000
--- a/include/nvgpu/acr/acr_flcnbl.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-#ifndef NVGPU_ACR_FLCNBL_H
-#define NVGPU_ACR_FLCNBL_H
-#include <nvgpu/flcnif_cmn.h>
-#ifndef NVGPU_ACR_H
-#warning "acr_flcnbl.h not included from nvgpu_acr.h!" \
-        "Include nvgpu_acr.h instead of acr_xxx.h to get access to ACR interfaces"
-#endif
-/*
- * Structure used by the boot-loader to load the rest of the code. This has
- * to be filled by NVGPU and copied into DMEM at offset provided in the
- * hsflcn_bl_desc.bl_desc_dmem_load_off.
- */
-struct flcn_bl_dmem_desc {
-        u32    reserved[4];        /*Should be the first element..*/
-        u32    signature[4];        /*Should be the first element..*/
-        u32    ctx_dma;
-        u32    code_dma_base;
-        u32    non_sec_code_off;
-        u32    non_sec_code_size;
-        u32    sec_code_off;
-        u32    sec_code_size;
-        u32    code_entry_point;
-        u32    data_dma_base;
-        u32    data_size;
-        u32    code_dma_base1;
-        u32    data_dma_base1;
-};
-struct flcn_bl_dmem_desc_v1 {
-        u32    reserved[4];        /*Should be the first element..*/
-        u32    signature[4];        /*Should be the first element..*/
-        u32    ctx_dma;
-        struct falc_u64 code_dma_base;
-        u32    non_sec_code_off;
-        u32    non_sec_code_size;
-        u32    sec_code_off;
-        u32    sec_code_size;
-        u32    code_entry_point;
-        struct falc_u64 data_dma_base;
-        u32    data_size;
-        u32 argc;
-        u32 argv;
-};
-/*
- * The header used by NVGPU to figure out code and data sections of bootloader
- *
- * bl_code_off        - Offset of code section in the image
- * bl_code_size          - Size of code section in the image
- * bl_data_off        - Offset of data section in the image
- * bl_data_size          - Size of data section in the image
- */
-struct flcn_bl_img_hdr {
-        u32 bl_code_off;
-        u32 bl_code_size;
-        u32 bl_data_off;
-        u32 bl_data_size;
-};
-/*
- * The descriptor used by NVGPU to figure out the requirements of bootloader
- *
- * bl_start_tag - Starting tag of bootloader
- * bl_desc_dmem_load_off - Dmem offset where _def_rm_flcn_bl_dmem_desc
- * to be loaded
- * bl_img_hdr - Description of the image
- */
-struct hsflcn_bl_desc {
-        u32 bl_start_tag;
-        u32 bl_desc_dmem_load_off;
-        struct flcn_bl_img_hdr bl_img_hdr;
-};
-/*
- * Legacy structure used by the current PMU/DPU bootloader.
- */
-struct loader_config {
-        u32 dma_idx;
-        u32 code_dma_base;     /* upper 32-bits of 40-bit dma address */
-        u32 code_size_total;
-        u32 code_size_to_load;
-        u32 code_entry_point;
-        u32 data_dma_base;     /* upper 32-bits of 40-bit dma address */
-        u32 data_size;         /* initialized data of the application  */
-        u32 overlay_dma_base;  /* upper 32-bits of the 40-bit dma address */
-        u32 argc;
-        u32 argv;
-        u16 code_dma_base1;    /* upper 7 bits of 47-bit dma address */
-        u16 data_dma_base1;    /* upper 7 bits of 47-bit dma address */
-        u16 overlay_dma_base1; /* upper 7 bits of the 47-bit dma address */
-};
-struct loader_config_v1 {
-        u32 reserved;
-        u32 dma_idx;
-        struct falc_u64 code_dma_base;
-        u32 code_size_total;
-        u32 code_size_to_load;
-        u32 code_entry_point;
-        struct falc_u64 data_dma_base;
-        u32 data_size;
-        struct falc_u64 overlay_dma_base;
-        u32 argc;
-        u32 argv;
-};
-/*
- * Union of all supported structures used by bootloaders.
- */
-union flcn_bl_generic_desc {
-        struct flcn_bl_dmem_desc bl_dmem_desc;
-        struct loader_config loader_cfg;
-};
-union flcn_bl_generic_desc_v1 {
-        struct flcn_bl_dmem_desc_v1 bl_dmem_desc_v1;
-        struct loader_config_v1 loader_cfg_v1;
-};
-#endif /* NVGPU_ACR_FLCNBL_H */

diff --git a/include/nvgpu/acr/acr_flcnbl.h b/include/nvgpu/acr/acr_flcnbl.h deleted file mode 100644 index ad697b2..0000000 --- a/include/nvgpu/acr/acr_flcnbl.h +++ /dev/null
@@ -1,144 +0,0 @@
1	/*
2	* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:
10	*
11	* The above copyright notice and this permission notice shall be included in
12	* all copies or substantial portions of the Software.
13	*
14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20	* DEALINGS IN THE SOFTWARE.
21	*/
22	#ifndef NVGPU_ACR_FLCNBL_H
23	#define NVGPU_ACR_FLCNBL_H
24
25	#include <nvgpu/flcnif_cmn.h>
26
27	#ifndef NVGPU_ACR_H
28	#warning "acr_flcnbl.h not included from nvgpu_acr.h!" \
29	"Include nvgpu_acr.h instead of acr_xxx.h to get access to ACR interfaces"
30	#endif
31
32	/*
33	* Structure used by the boot-loader to load the rest of the code. This has
34	* to be filled by NVGPU and copied into DMEM at offset provided in the
35	* hsflcn_bl_desc.bl_desc_dmem_load_off.
36	*/
37	struct flcn_bl_dmem_desc {
38	u32 reserved[4]; /Should be the first element../
39	u32 signature[4]; /Should be the first element../
40	u32 ctx_dma;
41	u32 code_dma_base;
42	u32 non_sec_code_off;
43	u32 non_sec_code_size;
44	u32 sec_code_off;
45	u32 sec_code_size;
46	u32 code_entry_point;
47	u32 data_dma_base;
48	u32 data_size;
49	u32 code_dma_base1;
50	u32 data_dma_base1;
51	};
52
53	struct flcn_bl_dmem_desc_v1 {
54	u32 reserved[4]; /Should be the first element../
55	u32 signature[4]; /Should be the first element../
56	u32 ctx_dma;
57	struct falc_u64 code_dma_base;
58	u32 non_sec_code_off;
59	u32 non_sec_code_size;
60	u32 sec_code_off;
61	u32 sec_code_size;
62	u32 code_entry_point;
63	struct falc_u64 data_dma_base;
64	u32 data_size;
65	u32 argc;
66	u32 argv;
67	};
68
69	/*
70	* The header used by NVGPU to figure out code and data sections of bootloader
71	*
72	* bl_code_off - Offset of code section in the image
73	* bl_code_size - Size of code section in the image
74	* bl_data_off - Offset of data section in the image
75	* bl_data_size - Size of data section in the image
76	*/
77	struct flcn_bl_img_hdr {
78	u32 bl_code_off;
79	u32 bl_code_size;
80	u32 bl_data_off;
81	u32 bl_data_size;
82	};
83
84	/*
85	* The descriptor used by NVGPU to figure out the requirements of bootloader
86	*
87	* bl_start_tag - Starting tag of bootloader
88	* bl_desc_dmem_load_off - Dmem offset where _def_rm_flcn_bl_dmem_desc
89	* to be loaded
90	* bl_img_hdr - Description of the image
91	*/
92	struct hsflcn_bl_desc {
93	u32 bl_start_tag;
94	u32 bl_desc_dmem_load_off;
95	struct flcn_bl_img_hdr bl_img_hdr;
96	};
97
98	/*
99	* Legacy structure used by the current PMU/DPU bootloader.
100	*/
101	struct loader_config {
102	u32 dma_idx;
103	u32 code_dma_base; /* upper 32-bits of 40-bit dma address */
104	u32 code_size_total;
105	u32 code_size_to_load;
106	u32 code_entry_point;
107	u32 data_dma_base; /* upper 32-bits of 40-bit dma address */
108	u32 data_size; /* initialized data of the application */
109	u32 overlay_dma_base; /* upper 32-bits of the 40-bit dma address */
110	u32 argc;
111	u32 argv;
112	u16 code_dma_base1; /* upper 7 bits of 47-bit dma address */
113	u16 data_dma_base1; /* upper 7 bits of 47-bit dma address */
114	u16 overlay_dma_base1; /* upper 7 bits of the 47-bit dma address */
115	};
116
117	struct loader_config_v1 {
118	u32 reserved;
119	u32 dma_idx;
120	struct falc_u64 code_dma_base;
121	u32 code_size_total;
122	u32 code_size_to_load;
123	u32 code_entry_point;
124	struct falc_u64 data_dma_base;
125	u32 data_size;
126	struct falc_u64 overlay_dma_base;
127	u32 argc;
128	u32 argv;
129	};
130
131	/*
132	* Union of all supported structures used by bootloaders.
133	*/
134	union flcn_bl_generic_desc {
135	struct flcn_bl_dmem_desc bl_dmem_desc;
136	struct loader_config loader_cfg;
137	};
138
139	union flcn_bl_generic_desc_v1 {
140	struct flcn_bl_dmem_desc_v1 bl_dmem_desc_v1;
141	struct loader_config_v1 loader_cfg_v1;
142	};
143
144	#endif /* NVGPU_ACR_FLCNBL_H */