diff options
Diffstat (limited to 'include/gk20a/regops_gk20a.h')
| -rw-r--r-- | include/gk20a/regops_gk20a.h | 90 |
1 files changed, 0 insertions, 90 deletions
diff --git a/include/gk20a/regops_gk20a.h b/include/gk20a/regops_gk20a.h deleted file mode 100644 index 9670587..0000000 --- a/include/gk20a/regops_gk20a.h +++ /dev/null | |||
| @@ -1,90 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Tegra GK20A GPU Debugger Driver Register Ops | ||
| 3 | * | ||
| 4 | * Copyright (c) 2013-2018, NVIDIA CORPORATION. All rights reserved. | ||
| 5 | * | ||
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
| 7 | * copy of this software and associated documentation files (the "Software"), | ||
| 8 | * to deal in the Software without restriction, including without limitation | ||
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
| 10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
| 11 | * Software is furnished to do so, subject to the following conditions: | ||
| 12 | * | ||
| 13 | * The above copyright notice and this permission notice shall be included in | ||
| 14 | * all copies or substantial portions of the Software. | ||
| 15 | * | ||
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
| 21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
| 22 | * DEALINGS IN THE SOFTWARE. | ||
| 23 | */ | ||
| 24 | #ifndef REGOPS_GK20A_H | ||
| 25 | #define REGOPS_GK20A_H | ||
| 26 | |||
| 27 | /* | ||
| 28 | * Register operations | ||
| 29 | * All operations are targeted towards first channel | ||
| 30 | * attached to debug session | ||
| 31 | */ | ||
| 32 | /* valid op values */ | ||
| 33 | #define NVGPU_DBG_REG_OP_READ_32 (0x00000000) | ||
| 34 | #define NVGPU_DBG_REG_OP_WRITE_32 (0x00000001) | ||
| 35 | #define NVGPU_DBG_REG_OP_READ_64 (0x00000002) | ||
| 36 | #define NVGPU_DBG_REG_OP_WRITE_64 (0x00000003) | ||
| 37 | /* note: 8b ops are unsupported */ | ||
| 38 | #define NVGPU_DBG_REG_OP_READ_08 (0x00000004) | ||
| 39 | #define NVGPU_DBG_REG_OP_WRITE_08 (0x00000005) | ||
| 40 | |||
| 41 | /* valid type values */ | ||
| 42 | #define NVGPU_DBG_REG_OP_TYPE_GLOBAL (0x00000000) | ||
| 43 | #define NVGPU_DBG_REG_OP_TYPE_GR_CTX (0x00000001) | ||
| 44 | #define NVGPU_DBG_REG_OP_TYPE_GR_CTX_TPC (0x00000002) | ||
| 45 | #define NVGPU_DBG_REG_OP_TYPE_GR_CTX_SM (0x00000004) | ||
| 46 | #define NVGPU_DBG_REG_OP_TYPE_GR_CTX_CROP (0x00000008) | ||
| 47 | #define NVGPU_DBG_REG_OP_TYPE_GR_CTX_ZROP (0x00000010) | ||
| 48 | /*#define NVGPU_DBG_REG_OP_TYPE_FB (0x00000020)*/ | ||
| 49 | #define NVGPU_DBG_REG_OP_TYPE_GR_CTX_QUAD (0x00000040) | ||
| 50 | |||
| 51 | /* valid status values */ | ||
| 52 | #define NVGPU_DBG_REG_OP_STATUS_SUCCESS (0x00000000) | ||
| 53 | #define NVGPU_DBG_REG_OP_STATUS_INVALID_OP (0x00000001) | ||
| 54 | #define NVGPU_DBG_REG_OP_STATUS_INVALID_TYPE (0x00000002) | ||
| 55 | #define NVGPU_DBG_REG_OP_STATUS_INVALID_OFFSET (0x00000004) | ||
| 56 | #define NVGPU_DBG_REG_OP_STATUS_UNSUPPORTED_OP (0x00000008) | ||
| 57 | #define NVGPU_DBG_REG_OP_STATUS_INVALID_MASK (0x00000010) | ||
| 58 | |||
| 59 | struct nvgpu_dbg_reg_op { | ||
| 60 | u8 op; | ||
| 61 | u8 type; | ||
| 62 | u8 status; | ||
| 63 | u8 quad; | ||
| 64 | u32 group_mask; | ||
| 65 | u32 sub_group_mask; | ||
| 66 | u32 offset; | ||
| 67 | u32 value_lo; | ||
| 68 | u32 value_hi; | ||
| 69 | u32 and_n_mask_lo; | ||
| 70 | u32 and_n_mask_hi; | ||
| 71 | }; | ||
| 72 | |||
| 73 | struct regop_offset_range { | ||
| 74 | u32 base:24; | ||
| 75 | u32 count:8; | ||
| 76 | }; | ||
| 77 | |||
| 78 | int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s, | ||
| 79 | struct nvgpu_dbg_reg_op *ops, | ||
| 80 | u64 num_ops, | ||
| 81 | bool *is_current_ctx); | ||
| 82 | |||
| 83 | /* turn seriously unwieldy names -> something shorter */ | ||
| 84 | #define REGOP(x) NVGPU_DBG_REG_OP_##x | ||
| 85 | |||
| 86 | bool reg_op_is_gr_ctx(u8 type); | ||
| 87 | bool reg_op_is_read(u8 op); | ||
| 88 | bool is_bar0_global_offset_whitelisted_gk20a(struct gk20a *g, u32 offset); | ||
| 89 | |||
| 90 | #endif /* REGOPS_GK20A_H */ | ||