diff options
Diffstat (limited to 'include/gk20a/hw_trim_gk20a.h')
-rw-r--r-- | include/gk20a/hw_trim_gk20a.h | 315 |
1 files changed, 315 insertions, 0 deletions
diff --git a/include/gk20a/hw_trim_gk20a.h b/include/gk20a/hw_trim_gk20a.h new file mode 100644 index 0000000..f28c21f --- /dev/null +++ b/include/gk20a/hw_trim_gk20a.h | |||
@@ -0,0 +1,315 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_trim_gk20a_h_ | ||
57 | #define _hw_trim_gk20a_h_ | ||
58 | |||
59 | static inline u32 trim_sys_gpcpll_cfg_r(void) | ||
60 | { | ||
61 | return 0x00137000U; | ||
62 | } | ||
63 | static inline u32 trim_sys_gpcpll_cfg_enable_m(void) | ||
64 | { | ||
65 | return 0x1U << 0U; | ||
66 | } | ||
67 | static inline u32 trim_sys_gpcpll_cfg_enable_v(u32 r) | ||
68 | { | ||
69 | return (r >> 0U) & 0x1U; | ||
70 | } | ||
71 | static inline u32 trim_sys_gpcpll_cfg_enable_no_f(void) | ||
72 | { | ||
73 | return 0x0U; | ||
74 | } | ||
75 | static inline u32 trim_sys_gpcpll_cfg_enable_yes_f(void) | ||
76 | { | ||
77 | return 0x1U; | ||
78 | } | ||
79 | static inline u32 trim_sys_gpcpll_cfg_iddq_m(void) | ||
80 | { | ||
81 | return 0x1U << 1U; | ||
82 | } | ||
83 | static inline u32 trim_sys_gpcpll_cfg_iddq_v(u32 r) | ||
84 | { | ||
85 | return (r >> 1U) & 0x1U; | ||
86 | } | ||
87 | static inline u32 trim_sys_gpcpll_cfg_iddq_power_on_v(void) | ||
88 | { | ||
89 | return 0x00000000U; | ||
90 | } | ||
91 | static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_m(void) | ||
92 | { | ||
93 | return 0x1U << 4U; | ||
94 | } | ||
95 | static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_on_f(void) | ||
96 | { | ||
97 | return 0x0U; | ||
98 | } | ||
99 | static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_off_f(void) | ||
100 | { | ||
101 | return 0x10U; | ||
102 | } | ||
103 | static inline u32 trim_sys_gpcpll_cfg_pll_lock_v(u32 r) | ||
104 | { | ||
105 | return (r >> 17U) & 0x1U; | ||
106 | } | ||
107 | static inline u32 trim_sys_gpcpll_cfg_pll_lock_true_f(void) | ||
108 | { | ||
109 | return 0x20000U; | ||
110 | } | ||
111 | static inline u32 trim_sys_gpcpll_coeff_r(void) | ||
112 | { | ||
113 | return 0x00137004U; | ||
114 | } | ||
115 | static inline u32 trim_sys_gpcpll_coeff_mdiv_f(u32 v) | ||
116 | { | ||
117 | return (v & 0xffU) << 0U; | ||
118 | } | ||
119 | static inline u32 trim_sys_gpcpll_coeff_mdiv_m(void) | ||
120 | { | ||
121 | return 0xffU << 0U; | ||
122 | } | ||
123 | static inline u32 trim_sys_gpcpll_coeff_mdiv_v(u32 r) | ||
124 | { | ||
125 | return (r >> 0U) & 0xffU; | ||
126 | } | ||
127 | static inline u32 trim_sys_gpcpll_coeff_ndiv_f(u32 v) | ||
128 | { | ||
129 | return (v & 0xffU) << 8U; | ||
130 | } | ||
131 | static inline u32 trim_sys_gpcpll_coeff_ndiv_m(void) | ||
132 | { | ||
133 | return 0xffU << 8U; | ||
134 | } | ||
135 | static inline u32 trim_sys_gpcpll_coeff_ndiv_v(u32 r) | ||
136 | { | ||
137 | return (r >> 8U) & 0xffU; | ||
138 | } | ||
139 | static inline u32 trim_sys_gpcpll_coeff_pldiv_f(u32 v) | ||
140 | { | ||
141 | return (v & 0x3fU) << 16U; | ||
142 | } | ||
143 | static inline u32 trim_sys_gpcpll_coeff_pldiv_m(void) | ||
144 | { | ||
145 | return 0x3fU << 16U; | ||
146 | } | ||
147 | static inline u32 trim_sys_gpcpll_coeff_pldiv_v(u32 r) | ||
148 | { | ||
149 | return (r >> 16U) & 0x3fU; | ||
150 | } | ||
151 | static inline u32 trim_sys_sel_vco_r(void) | ||
152 | { | ||
153 | return 0x00137100U; | ||
154 | } | ||
155 | static inline u32 trim_sys_sel_vco_gpc2clk_out_m(void) | ||
156 | { | ||
157 | return 0x1U << 0U; | ||
158 | } | ||
159 | static inline u32 trim_sys_sel_vco_gpc2clk_out_init_v(void) | ||
160 | { | ||
161 | return 0x00000000U; | ||
162 | } | ||
163 | static inline u32 trim_sys_sel_vco_gpc2clk_out_init_f(void) | ||
164 | { | ||
165 | return 0x0U; | ||
166 | } | ||
167 | static inline u32 trim_sys_sel_vco_gpc2clk_out_bypass_f(void) | ||
168 | { | ||
169 | return 0x0U; | ||
170 | } | ||
171 | static inline u32 trim_sys_sel_vco_gpc2clk_out_vco_f(void) | ||
172 | { | ||
173 | return 0x1U; | ||
174 | } | ||
175 | static inline u32 trim_sys_gpc2clk_out_r(void) | ||
176 | { | ||
177 | return 0x00137250U; | ||
178 | } | ||
179 | static inline u32 trim_sys_gpc2clk_out_bypdiv_s(void) | ||
180 | { | ||
181 | return 6U; | ||
182 | } | ||
183 | static inline u32 trim_sys_gpc2clk_out_bypdiv_f(u32 v) | ||
184 | { | ||
185 | return (v & 0x3fU) << 0U; | ||
186 | } | ||
187 | static inline u32 trim_sys_gpc2clk_out_bypdiv_m(void) | ||
188 | { | ||
189 | return 0x3fU << 0U; | ||
190 | } | ||
191 | static inline u32 trim_sys_gpc2clk_out_bypdiv_v(u32 r) | ||
192 | { | ||
193 | return (r >> 0U) & 0x3fU; | ||
194 | } | ||
195 | static inline u32 trim_sys_gpc2clk_out_bypdiv_by31_f(void) | ||
196 | { | ||
197 | return 0x3cU; | ||
198 | } | ||
199 | static inline u32 trim_sys_gpc2clk_out_vcodiv_s(void) | ||
200 | { | ||
201 | return 6U; | ||
202 | } | ||
203 | static inline u32 trim_sys_gpc2clk_out_vcodiv_f(u32 v) | ||
204 | { | ||
205 | return (v & 0x3fU) << 8U; | ||
206 | } | ||
207 | static inline u32 trim_sys_gpc2clk_out_vcodiv_m(void) | ||
208 | { | ||
209 | return 0x3fU << 8U; | ||
210 | } | ||
211 | static inline u32 trim_sys_gpc2clk_out_vcodiv_v(u32 r) | ||
212 | { | ||
213 | return (r >> 8U) & 0x3fU; | ||
214 | } | ||
215 | static inline u32 trim_sys_gpc2clk_out_vcodiv_by1_f(void) | ||
216 | { | ||
217 | return 0x0U; | ||
218 | } | ||
219 | static inline u32 trim_sys_gpc2clk_out_sdiv14_m(void) | ||
220 | { | ||
221 | return 0x1U << 31U; | ||
222 | } | ||
223 | static inline u32 trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f(void) | ||
224 | { | ||
225 | return 0x80000000U; | ||
226 | } | ||
227 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_r(u32 i) | ||
228 | { | ||
229 | return 0x00134124U + i*512U; | ||
230 | } | ||
231 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(u32 v) | ||
232 | { | ||
233 | return (v & 0x3fffU) << 0U; | ||
234 | } | ||
235 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f(void) | ||
236 | { | ||
237 | return 0x10000U; | ||
238 | } | ||
239 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_enable_asserted_f(void) | ||
240 | { | ||
241 | return 0x100000U; | ||
242 | } | ||
243 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f(void) | ||
244 | { | ||
245 | return 0x1000000U; | ||
246 | } | ||
247 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_r(u32 i) | ||
248 | { | ||
249 | return 0x00134128U + i*512U; | ||
250 | } | ||
251 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(u32 r) | ||
252 | { | ||
253 | return (r >> 0U) & 0xfffffU; | ||
254 | } | ||
255 | static inline u32 trim_sys_gpcpll_cfg2_r(void) | ||
256 | { | ||
257 | return 0x0013700cU; | ||
258 | } | ||
259 | static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_f(u32 v) | ||
260 | { | ||
261 | return (v & 0xffU) << 24U; | ||
262 | } | ||
263 | static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_m(void) | ||
264 | { | ||
265 | return 0xffU << 24U; | ||
266 | } | ||
267 | static inline u32 trim_sys_gpcpll_cfg3_r(void) | ||
268 | { | ||
269 | return 0x00137018U; | ||
270 | } | ||
271 | static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_f(u32 v) | ||
272 | { | ||
273 | return (v & 0xffU) << 16U; | ||
274 | } | ||
275 | static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_m(void) | ||
276 | { | ||
277 | return 0xffU << 16U; | ||
278 | } | ||
279 | static inline u32 trim_sys_gpcpll_ndiv_slowdown_r(void) | ||
280 | { | ||
281 | return 0x0013701cU; | ||
282 | } | ||
283 | static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m(void) | ||
284 | { | ||
285 | return 0x1U << 22U; | ||
286 | } | ||
287 | static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_yes_f(void) | ||
288 | { | ||
289 | return 0x400000U; | ||
290 | } | ||
291 | static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_no_f(void) | ||
292 | { | ||
293 | return 0x0U; | ||
294 | } | ||
295 | static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(void) | ||
296 | { | ||
297 | return 0x1U << 31U; | ||
298 | } | ||
299 | static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f(void) | ||
300 | { | ||
301 | return 0x80000000U; | ||
302 | } | ||
303 | static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_no_f(void) | ||
304 | { | ||
305 | return 0x0U; | ||
306 | } | ||
307 | static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r(void) | ||
308 | { | ||
309 | return 0x001328a0U; | ||
310 | } | ||
311 | static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_pll_dynramp_done_synced_v(u32 r) | ||
312 | { | ||
313 | return (r >> 24U) & 0x1U; | ||
314 | } | ||
315 | #endif | ||