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diff --git a/include/gk20a/gr_pri_gk20a.h b/include/gk20a/gr_pri_gk20a.h
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1/*
2 * GK20A Graphics Context Pri Register Addressing
3 *
4 * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24#ifndef GR_PRI_GK20A_H
25#define GR_PRI_GK20A_H
26
27/*
28 * These convenience macros are generally for use in the management/modificaiton
29 * of the context state store for gr/compute contexts.
30 */
31
32/*
33 * GPC pri addressing
34 */
35static inline u32 pri_gpccs_addr_width(void)
36{
37 return 15; /*from where?*/
38}
39static inline u32 pri_gpccs_addr_mask(u32 addr)
40{
41 return addr & ((1 << pri_gpccs_addr_width()) - 1);
42}
43static inline u32 pri_gpc_addr(struct gk20a *g, u32 addr, u32 gpc)
44{
45 u32 gpc_base = nvgpu_get_litter_value(g, GPU_LIT_GPC_BASE);
46 u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
47 return gpc_base + (gpc * gpc_stride) + addr;
48}
49static inline bool pri_is_gpc_addr_shared(struct gk20a *g, u32 addr)
50{
51 u32 gpc_shared_base = nvgpu_get_litter_value(g, GPU_LIT_GPC_SHARED_BASE);
52 u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
53 return (addr >= gpc_shared_base) &&
54 (addr < gpc_shared_base + gpc_stride);
55}
56static inline bool pri_is_gpc_addr(struct gk20a *g, u32 addr)
57{
58 u32 gpc_base = nvgpu_get_litter_value(g, GPU_LIT_GPC_BASE);
59 u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
60 u32 num_gpcs = nvgpu_get_litter_value(g, GPU_LIT_NUM_GPCS);
61 return ((addr >= gpc_base) &&
62 (addr < gpc_base + num_gpcs * gpc_stride)) ||
63 pri_is_gpc_addr_shared(g, addr);
64}
65static inline u32 pri_get_gpc_num(struct gk20a *g, u32 addr)
66{
67 u32 i, start;
68 u32 num_gpcs = nvgpu_get_litter_value(g, GPU_LIT_NUM_GPCS);
69 u32 gpc_base = nvgpu_get_litter_value(g, GPU_LIT_GPC_BASE);
70 u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
71 for (i = 0; i < num_gpcs; i++) {
72 start = gpc_base + (i * gpc_stride);
73 if ((addr >= start) && (addr < (start + gpc_stride)))
74 return i;
75 }
76 return 0;
77}
78
79/*
80 * PPC pri addressing
81 */
82static inline bool pri_is_ppc_addr_shared(struct gk20a *g, u32 addr)
83{
84 u32 ppc_in_gpc_shared_base = nvgpu_get_litter_value(g,
85 GPU_LIT_PPC_IN_GPC_SHARED_BASE);
86 u32 ppc_in_gpc_stride = nvgpu_get_litter_value(g,
87 GPU_LIT_PPC_IN_GPC_STRIDE);
88
89 return ((addr >= ppc_in_gpc_shared_base) &&
90 (addr < (ppc_in_gpc_shared_base + ppc_in_gpc_stride)));
91}
92
93static inline bool pri_is_ppc_addr(struct gk20a *g, u32 addr)
94{
95 u32 ppc_in_gpc_base = nvgpu_get_litter_value(g,
96 GPU_LIT_PPC_IN_GPC_BASE);
97 u32 num_pes_per_gpc = nvgpu_get_litter_value(g,
98 GPU_LIT_NUM_PES_PER_GPC);
99 u32 ppc_in_gpc_stride = nvgpu_get_litter_value(g,
100 GPU_LIT_PPC_IN_GPC_STRIDE);
101
102 return ((addr >= ppc_in_gpc_base) &&
103 (addr < ppc_in_gpc_base + num_pes_per_gpc * ppc_in_gpc_stride))
104 || pri_is_ppc_addr_shared(g, addr);
105}
106
107/*
108 * TPC pri addressing
109 */
110static inline u32 pri_tpccs_addr_width(void)
111{
112 return 11; /* from where? */
113}
114static inline u32 pri_tpccs_addr_mask(u32 addr)
115{
116 return addr & ((1 << pri_tpccs_addr_width()) - 1);
117}
118static inline u32 pri_fbpa_addr_mask(struct gk20a *g, u32 addr)
119{
120 return addr & (nvgpu_get_litter_value(g, GPU_LIT_FBPA_STRIDE) - 1);
121}
122static inline u32 pri_tpc_addr(struct gk20a *g, u32 addr, u32 gpc, u32 tpc)
123{
124 u32 gpc_base = nvgpu_get_litter_value(g, GPU_LIT_GPC_BASE);
125 u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
126 u32 tpc_in_gpc_base = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_BASE);
127 u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
128 return gpc_base + (gpc * gpc_stride) +
129 tpc_in_gpc_base + (tpc * tpc_in_gpc_stride) +
130 addr;
131}
132static inline bool pri_is_tpc_addr_shared(struct gk20a *g, u32 addr)
133{
134 u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
135 u32 tpc_in_gpc_shared_base = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_SHARED_BASE);
136 return (addr >= tpc_in_gpc_shared_base) &&
137 (addr < (tpc_in_gpc_shared_base +
138 tpc_in_gpc_stride));
139}
140static inline u32 pri_fbpa_addr(struct gk20a *g, u32 addr, u32 fbpa)
141{
142 return (nvgpu_get_litter_value(g, GPU_LIT_FBPA_BASE) + addr +
143 (fbpa * nvgpu_get_litter_value(g, GPU_LIT_FBPA_STRIDE)));
144}
145static inline bool pri_is_fbpa_addr_shared(struct gk20a *g, u32 addr)
146{
147 u32 fbpa_shared_base = nvgpu_get_litter_value(g, GPU_LIT_FBPA_SHARED_BASE);
148 u32 fbpa_stride = nvgpu_get_litter_value(g, GPU_LIT_FBPA_STRIDE);
149 return ((addr >= fbpa_shared_base) &&
150 (addr < (fbpa_shared_base + fbpa_stride)));
151}
152static inline bool pri_is_fbpa_addr(struct gk20a *g, u32 addr)
153{
154 u32 fbpa_base = nvgpu_get_litter_value(g, GPU_LIT_FBPA_BASE);
155 u32 fbpa_stride = nvgpu_get_litter_value(g, GPU_LIT_FBPA_STRIDE);
156 u32 num_fbpas = nvgpu_get_litter_value(g, GPU_LIT_NUM_FBPAS);
157 return (((addr >= fbpa_base) &&
158 (addr < (fbpa_base + num_fbpas * fbpa_stride)))
159 || pri_is_fbpa_addr_shared(g, addr));
160}
161/*
162 * BE pri addressing
163 */
164static inline u32 pri_becs_addr_width(void)
165{
166 return 10;/* from where? */
167}
168static inline u32 pri_becs_addr_mask(u32 addr)
169{
170 return addr & ((1 << pri_becs_addr_width()) - 1);
171}
172static inline bool pri_is_be_addr_shared(struct gk20a *g, u32 addr)
173{
174 u32 rop_shared_base = nvgpu_get_litter_value(g, GPU_LIT_ROP_SHARED_BASE);
175 u32 rop_stride = nvgpu_get_litter_value(g, GPU_LIT_ROP_STRIDE);
176 return (addr >= rop_shared_base) &&
177 (addr < rop_shared_base + rop_stride);
178}
179static inline u32 pri_be_shared_addr(struct gk20a *g, u32 addr)
180{
181 u32 rop_shared_base = nvgpu_get_litter_value(g, GPU_LIT_ROP_SHARED_BASE);
182 return rop_shared_base + pri_becs_addr_mask(addr);
183}
184static inline bool pri_is_be_addr(struct gk20a *g, u32 addr)
185{
186 u32 rop_base = nvgpu_get_litter_value(g, GPU_LIT_ROP_BASE);
187 u32 rop_stride = nvgpu_get_litter_value(g, GPU_LIT_ROP_STRIDE);
188 return ((addr >= rop_base) &&
189 (addr < rop_base + g->ltc_count * rop_stride)) ||
190 pri_is_be_addr_shared(g, addr);
191}
192
193static inline u32 pri_get_be_num(struct gk20a *g, u32 addr)
194{
195 u32 i, start;
196 u32 num_fbps = nvgpu_get_litter_value(g, GPU_LIT_NUM_FBPS);
197 u32 rop_base = nvgpu_get_litter_value(g, GPU_LIT_ROP_BASE);
198 u32 rop_stride = nvgpu_get_litter_value(g, GPU_LIT_ROP_STRIDE);
199 for (i = 0; i < num_fbps; i++) {
200 start = rop_base + (i * rop_stride);
201 if ((addr >= start) && (addr < (start + rop_stride)))
202 return i;
203 }
204 return 0;
205}
206
207/*
208 * PPC pri addressing
209 */
210static inline u32 pri_ppccs_addr_width(void)
211{
212 return 9; /* from where? */
213}
214static inline u32 pri_ppccs_addr_mask(u32 addr)
215{
216 return addr & ((1 << pri_ppccs_addr_width()) - 1);
217}
218static inline u32 pri_ppc_addr(struct gk20a *g, u32 addr, u32 gpc, u32 ppc)
219{
220 u32 gpc_base = nvgpu_get_litter_value(g, GPU_LIT_GPC_BASE);
221 u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
222 u32 ppc_in_gpc_base = nvgpu_get_litter_value(g, GPU_LIT_PPC_IN_GPC_BASE);
223 u32 ppc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_PPC_IN_GPC_STRIDE);
224 return gpc_base + (gpc * gpc_stride) +
225 ppc_in_gpc_base + (ppc * ppc_in_gpc_stride) + addr;
226}
227
228enum ctxsw_addr_type {
229 CTXSW_ADDR_TYPE_SYS = 0,
230 CTXSW_ADDR_TYPE_GPC = 1,
231 CTXSW_ADDR_TYPE_TPC = 2,
232 CTXSW_ADDR_TYPE_BE = 3,
233 CTXSW_ADDR_TYPE_PPC = 4,
234 CTXSW_ADDR_TYPE_LTCS = 5,
235 CTXSW_ADDR_TYPE_FBPA = 6,
236 CTXSW_ADDR_TYPE_EGPC = 7,
237 CTXSW_ADDR_TYPE_ETPC = 8,
238 CTXSW_ADDR_TYPE_ROP = 9,
239 CTXSW_ADDR_TYPE_FBP = 10,
240};
241
242#define PRI_BROADCAST_FLAGS_NONE 0U
243#define PRI_BROADCAST_FLAGS_GPC BIT32(0)
244#define PRI_BROADCAST_FLAGS_TPC BIT32(1)
245#define PRI_BROADCAST_FLAGS_BE BIT32(2)
246#define PRI_BROADCAST_FLAGS_PPC BIT32(3)
247#define PRI_BROADCAST_FLAGS_LTCS BIT32(4)
248#define PRI_BROADCAST_FLAGS_LTSS BIT32(5)
249#define PRI_BROADCAST_FLAGS_FBPA BIT32(6)
250#define PRI_BROADCAST_FLAGS_EGPC BIT32(7)
251#define PRI_BROADCAST_FLAGS_ETPC BIT32(8)
252#define PRI_BROADCAST_FLAGS_PMMGPC BIT32(9)
253#define PRI_BROADCAST_FLAGS_PMM_GPCS BIT32(10)
254#define PRI_BROADCAST_FLAGS_PMM_GPCGS_GPCTPCA BIT32(11)
255#define PRI_BROADCAST_FLAGS_PMM_GPCGS_GPCTPCB BIT32(12)
256#define PRI_BROADCAST_FLAGS_PMMFBP BIT32(13)
257#define PRI_BROADCAST_FLAGS_PMM_FBPS BIT32(14)
258#define PRI_BROADCAST_FLAGS_PMM_FBPGS_LTC BIT32(15)
259#define PRI_BROADCAST_FLAGS_PMM_FBPGS_ROP BIT32(16)
260
261#endif /* GR_PRI_GK20A_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-30 22:21:11 -0400