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-rw-r--r--include/gk20a/gr_gk20a.c108
1 files changed, 100 insertions, 8 deletions
diff --git a/include/gk20a/gr_gk20a.c b/include/gk20a/gr_gk20a.c
index 7bcf528..1eda853 100644
--- a/include/gk20a/gr_gk20a.c
+++ b/include/gk20a/gr_gk20a.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * GK20A Graphics 2 * GK20A Graphics
3 * 3 *
4 * Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2011-2023, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -121,6 +121,83 @@ int gr_gk20a_get_ctx_id(struct gk20a *g,
121 return 0; 121 return 0;
122} 122}
123 123
124void gk20a_gpccs_dump_falcon_stats(struct gk20a *g)
125{
126 unsigned int i;
127
128 nvgpu_err(g, "gr_gpc0_gpccs_falcon_irqstat : %d",
129 gk20a_readl(g, gr_gpc0_gpccs_falcon_irqstat_r()));
130 nvgpu_err(g, "gr_gpc0_gpccs_falcon_irqmode : %d",
131 gk20a_readl(g, gr_gpc0_gpccs_falcon_irqmode_r()));
132 nvgpu_err(g, "gr_gpc0_gpccs_falcon_irqmask : %d",
133 gk20a_readl(g, gr_gpc0_gpccs_falcon_irqmask_r()));
134 nvgpu_err(g, "gr_gpc0_gpccs_falcon_irqdest : %d",
135 gk20a_readl(g, gr_gpc0_gpccs_falcon_irqdest_r()));
136 nvgpu_err(g, "gr_gpc0_gpccs_falcon_debug1 : %d",
137 gk20a_readl(g, gr_gpc0_gpccs_falcon_debug1_r()));
138 nvgpu_err(g, "gr_gpc0_gpccs_falcon_debuginfo : %d",
139 gk20a_readl(g, gr_gpc0_gpccs_falcon_debuginfo_r()));
140 nvgpu_err(g, "gr_gpc0_gpccs_falcon_engctl : %d",
141 gk20a_readl(g, gr_gpc0_gpccs_falcon_engctl_r()));
142 nvgpu_err(g, "gr_gpc0_gpccs_falcon_curctx : %d",
143 gk20a_readl(g, gr_gpc0_gpccs_falcon_curctx_r()));
144 nvgpu_err(g, "gr_gpc0_gpccs_falcon_nxtctx : %d",
145 gk20a_readl(g, gr_gpc0_gpccs_falcon_nxtctx_r()));
146 nvgpu_err(g, "gr_gpc0_gpccs_ctxsw_status_1 : %d",
147 gk20a_readl(g, gr_gpc0_gpccs_ctxsw_status_1_r()));
148
149 for (i = 0; i < g->ops.gr.gpc0_gpccs_ctxsw_mailbox_size(); i++) {
150 nvgpu_err(g, "gr_gpc0_gpccs_ctxsw_mailbox_r(%d) : 0x%x",
151 i, gk20a_readl(g, gr_gpc0_gpccs_ctxsw_mailbox_r(i)));
152 }
153
154
155 gk20a_writel(g, gr_gpc0_gpccs_falcon_icd_cmd_r(),
156 gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f() |
157 gr_gpc0_gpccs_falcon_icd_cmd_idx_f(PMU_FALCON_REG_IMB));
158 nvgpu_err(g, "GPC0_GPCCS_FALCON_REG_IMB : 0x%x",
159 gk20a_readl(g, gr_gpc_gpccs_falcon_icd_rdata_r()));
160
161 gk20a_writel(g, gr_gpc0_gpccs_falcon_icd_cmd_r(),
162 gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f() |
163 gr_gpc0_gpccs_falcon_icd_cmd_idx_f(PMU_FALCON_REG_DMB));
164 nvgpu_err(g, "GPC0_GPCCS_FALCON_REG_DMB : 0x%x",
165 gk20a_readl(g, gr_gpc_gpccs_falcon_icd_rdata_r()));
166
167 gk20a_writel(g, gr_gpc0_gpccs_falcon_icd_cmd_r(),
168 gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f() |
169 gr_gpc0_gpccs_falcon_icd_cmd_idx_f(PMU_FALCON_REG_CSW));
170 nvgpu_err(g, "GPC0_GPCCS_FALCON_REG_CSW : 0x%x",
171 gk20a_readl(g, gr_gpc_gpccs_falcon_icd_rdata_r()));
172
173 gk20a_writel(g, gr_gpc0_gpccs_falcon_icd_cmd_r(),
174 gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f() |
175 gr_gpc0_gpccs_falcon_icd_cmd_idx_f(PMU_FALCON_REG_CTX));
176 nvgpu_err(g, "GPC0_GPCCS_FALCON_REG_CTX : 0x%x",
177 gk20a_readl(g, gr_gpc_gpccs_falcon_icd_rdata_r()));
178
179 gk20a_writel(g, gr_gpc0_gpccs_falcon_icd_cmd_r(),
180 gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f() |
181 gr_gpc0_gpccs_falcon_icd_cmd_idx_f(PMU_FALCON_REG_EXCI));
182 nvgpu_err(g, "GPC0_GPCCS_FALCON_REG_EXCI : 0x%x",
183 gk20a_readl(g, gr_gpc_gpccs_falcon_icd_rdata_r()));
184
185
186 for (i = 0; i < 4U; i++) {
187 gk20a_writel(g, gr_gpc0_gpccs_falcon_icd_cmd_r(),
188 gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f() |
189 gr_gpc0_gpccs_falcon_icd_cmd_idx_f(PMU_FALCON_REG_PC));
190 nvgpu_err(g, "GPC0_GPCCS_FALCON_REG_PC : 0x%x",
191 gk20a_readl(g, gr_gpc_gpccs_falcon_icd_rdata_r()));
192
193 gk20a_writel(g, gr_gpc0_gpccs_falcon_icd_cmd_r(),
194 gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f() |
195 gr_gpc0_gpccs_falcon_icd_cmd_idx_f(PMU_FALCON_REG_SP));
196 nvgpu_err(g, "GPC0_GPCCS_FALCON_REG_SP : 0x%x",
197 gk20a_readl(g, gr_gpc_gpccs_falcon_icd_rdata_r()));
198 }
199}
200
124void gk20a_fecs_dump_falcon_stats(struct gk20a *g) 201void gk20a_fecs_dump_falcon_stats(struct gk20a *g)
125{ 202{
126 unsigned int i; 203 unsigned int i;
@@ -527,6 +604,7 @@ int gr_gk20a_ctx_wait_ucode(struct gk20a *g, u32 mailbox_id,
527 "timeout waiting on mailbox=%d value=0x%08x", 604 "timeout waiting on mailbox=%d value=0x%08x",
528 mailbox_id, reg); 605 mailbox_id, reg);
529 gk20a_fecs_dump_falcon_stats(g); 606 gk20a_fecs_dump_falcon_stats(g);
607 gk20a_gpccs_dump_falcon_stats(g);
530 gk20a_gr_debug_dump(g); 608 gk20a_gr_debug_dump(g);
531 return -1; 609 return -1;
532 } else if (check == WAIT_UCODE_ERROR) { 610 } else if (check == WAIT_UCODE_ERROR) {
@@ -534,6 +612,7 @@ int gr_gk20a_ctx_wait_ucode(struct gk20a *g, u32 mailbox_id,
534 "ucode method failed on mailbox=%d value=0x%08x", 612 "ucode method failed on mailbox=%d value=0x%08x",
535 mailbox_id, reg); 613 mailbox_id, reg);
536 gk20a_fecs_dump_falcon_stats(g); 614 gk20a_fecs_dump_falcon_stats(g);
615 gk20a_gpccs_dump_falcon_stats(g);
537 return -1; 616 return -1;
538 } 617 }
539 618
@@ -1583,6 +1662,10 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g,
1583 sw_ctx_load->l[i].value); 1662 sw_ctx_load->l[i].value);
1584 } 1663 }
1585 1664
1665 if (g->ops.gr.disable_rd_coalesce) {
1666 g->ops.gr.disable_rd_coalesce(g);
1667 }
1668
1586 if (g->ops.gr.init_preemption_state) { 1669 if (g->ops.gr.init_preemption_state) {
1587 g->ops.gr.init_preemption_state(g); 1670 g->ops.gr.init_preemption_state(g);
1588 } 1671 }
@@ -4625,16 +4708,16 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
4625 g->ops.fb.init_cbc(g, gr); 4708 g->ops.fb.init_cbc(g, gr);
4626 } 4709 }
4627 4710
4628 if (g->ops.gr.disable_rd_coalesce) {
4629 g->ops.gr.disable_rd_coalesce(g);
4630 }
4631
4632 /* load ctx init */ 4711 /* load ctx init */
4633 for (i = 0; i < sw_ctx_load->count; i++) { 4712 for (i = 0; i < sw_ctx_load->count; i++) {
4634 gk20a_writel(g, sw_ctx_load->l[i].addr, 4713 gk20a_writel(g, sw_ctx_load->l[i].addr,
4635 sw_ctx_load->l[i].value); 4714 sw_ctx_load->l[i].value);
4636 } 4715 }
4637 4716
4717 if (g->ops.gr.disable_rd_coalesce) {
4718 g->ops.gr.disable_rd_coalesce(g);
4719 }
4720
4638 err = gr_gk20a_wait_idle(g, gk20a_get_gr_idle_timeout(g), 4721 err = gr_gk20a_wait_idle(g, gk20a_get_gr_idle_timeout(g),
4639 GR_IDLE_CHECK_DEFAULT); 4722 GR_IDLE_CHECK_DEFAULT);
4640 if (err != 0U) { 4723 if (err != 0U) {
@@ -5297,9 +5380,10 @@ int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch,
5297 } else if ((gr_fecs_intr & 5380 } else if ((gr_fecs_intr &
5298 gr_fecs_host_int_status_watchdog_active_f()) != 0U) { 5381 gr_fecs_host_int_status_watchdog_active_f()) != 0U) {
5299 /* currently, recovery is not initiated */ 5382 /* currently, recovery is not initiated */
5300 nvgpu_err(g, "fecs watchdog triggered for channel %u, " 5383 nvgpu_err(g, "fecs watchdog triggered for channel %u", chid);
5301 "cannot ctxsw anymore !!", chid);
5302 gk20a_fecs_dump_falcon_stats(g); 5384 gk20a_fecs_dump_falcon_stats(g);
5385 gk20a_gpccs_dump_falcon_stats(g);
5386 gk20a_gr_debug_dump(g);
5303 } else if ((gr_fecs_intr & 5387 } else if ((gr_fecs_intr &
5304 gr_fecs_host_int_status_ctxsw_intr_f(CTXSW_INTR0)) != 0U) { 5388 gr_fecs_host_int_status_ctxsw_intr_f(CTXSW_INTR0)) != 0U) {
5305 u32 mailbox_value = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(6)); 5389 u32 mailbox_value = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(6));
@@ -5321,8 +5405,9 @@ int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch,
5321 } else { 5405 } else {
5322 nvgpu_err(g, 5406 nvgpu_err(g,
5323 "unhandled fecs error interrupt 0x%08x for channel %u", 5407 "unhandled fecs error interrupt 0x%08x for channel %u",
5324 gr_fecs_intr, ch->chid); 5408 gr_fecs_intr, chid);
5325 gk20a_fecs_dump_falcon_stats(g); 5409 gk20a_fecs_dump_falcon_stats(g);
5410 gk20a_gpccs_dump_falcon_stats(g);
5326 } 5411 }
5327 5412
5328 gk20a_writel(g, gr_fecs_host_int_clear_r(), gr_fecs_intr); 5413 gk20a_writel(g, gr_fecs_host_int_clear_r(), gr_fecs_intr);
@@ -8851,6 +8936,10 @@ int gr_gk20a_wait_for_pause(struct gk20a *g, struct nvgpu_warpstate *w_state)
8851 u32 gpc, tpc, sm, sm_id; 8936 u32 gpc, tpc, sm, sm_id;
8852 u32 global_mask; 8937 u32 global_mask;
8853 8938
8939 if (!g->ops.gr.get_sm_no_lock_down_hww_global_esr_mask ||
8940 !g->ops.gr.lock_down_sm || !g->ops.gr.bpt_reg_info)
8941 return -EINVAL;
8942
8854 /* Wait for the SMs to reach full stop. This condition is: 8943 /* Wait for the SMs to reach full stop. This condition is:
8855 * 1) All SMs with valid warps must be in the trap handler (SM_IN_TRAP_MODE) 8944 * 1) All SMs with valid warps must be in the trap handler (SM_IN_TRAP_MODE)
8856 * 2) All SMs in the trap handler must have equivalent VALID and PAUSED warp 8945 * 2) All SMs in the trap handler must have equivalent VALID and PAUSED warp
@@ -8908,6 +8997,9 @@ int gr_gk20a_clear_sm_errors(struct gk20a *g)
8908 u32 global_esr; 8997 u32 global_esr;
8909 u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC); 8998 u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC);
8910 8999
9000 if (!g->ops.gr.get_sm_hww_global_esr || !g->ops.gr.clear_sm_hww)
9001 return -EINVAL;
9002
8911 for (gpc = 0; gpc < gr->gpc_count; gpc++) { 9003 for (gpc = 0; gpc < gr->gpc_count; gpc++) {
8912 9004
8913 /* check if any tpc has an exception */ 9005 /* check if any tpc has an exception */