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Diffstat (limited to 'include/gk20a/gk20a.c')
-rw-r--r--include/gk20a/gk20a.c595
1 files changed, 0 insertions, 595 deletions
diff --git a/include/gk20a/gk20a.c b/include/gk20a/gk20a.c
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index 1a11716..0000000
--- a/include/gk20a/gk20a.c
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1/*
2 * GK20A Graphics
3 *
4 * Copyright (c) 2011-2021, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#include <nvgpu/nvgpu_common.h>
26#include <nvgpu/kmem.h>
27#include <nvgpu/allocator.h>
28#include <nvgpu/timers.h>
29#include <nvgpu/soc.h>
30#include <nvgpu/enabled.h>
31#include <nvgpu/pmu.h>
32#include <nvgpu/gmmu.h>
33#include <nvgpu/ltc.h>
34#include <nvgpu/vidmem.h>
35#include <nvgpu/mm.h>
36#include <nvgpu/ctxsw_trace.h>
37#include <nvgpu/soc.h>
38#include <nvgpu/clk_arb.h>
39#include <nvgpu/therm.h>
40#include <nvgpu/mc.h>
41#include <nvgpu/channel_sync.h>
42#include <nvgpu/nvgpu_err.h>
43
44#include <trace/events/gk20a.h>
45
46#include "gk20a.h"
47
48#include "dbg_gpu_gk20a.h"
49#include "pstate/pstate.h"
50
51void __nvgpu_check_gpu_state(struct gk20a *g)
52{
53 u32 boot_0 = 0xffffffff;
54
55 boot_0 = nvgpu_mc_boot_0(g, NULL, NULL, NULL);
56 if (boot_0 == 0xffffffff) {
57 nvgpu_err(g, "GPU has disappeared from bus!!");
58 nvgpu_err(g, "Rebooting system!!");
59 nvgpu_kernel_restart(NULL);
60 }
61}
62
63void __gk20a_warn_on_no_regs(void)
64{
65 WARN_ONCE(1, "Attempted access to GPU regs after unmapping!");
66}
67
68static void gk20a_mask_interrupts(struct gk20a *g)
69{
70 if (g->ops.mc.intr_mask != NULL) {
71 g->ops.mc.intr_mask(g);
72 }
73
74 if (g->ops.mc.log_pending_intrs != NULL) {
75 g->ops.mc.log_pending_intrs(g);
76 }
77}
78
79int gk20a_prepare_poweroff(struct gk20a *g)
80{
81 int ret = 0;
82
83 nvgpu_log_fn(g, " ");
84
85 if (g->ops.fifo.channel_suspend) {
86 ret = g->ops.fifo.channel_suspend(g);
87 if (ret) {
88 return ret;
89 }
90 }
91
92 /* disable elpg before gr or fifo suspend */
93 if (g->ops.pmu.is_pmu_supported(g)) {
94 ret |= nvgpu_pmu_destroy(g);
95 }
96
97 if (nvgpu_is_enabled(g, NVGPU_SUPPORT_SEC2_RTOS)) {
98 ret |= nvgpu_sec2_destroy(g);
99 }
100
101 ret |= gk20a_gr_suspend(g);
102 ret |= nvgpu_mm_suspend(g);
103 ret |= gk20a_fifo_suspend(g);
104
105 gk20a_ce_suspend(g);
106
107 /* Disable GPCPLL */
108 if (g->ops.clk.suspend_clk_support) {
109 ret |= g->ops.clk.suspend_clk_support(g);
110 }
111
112 if (nvgpu_is_enabled(g, NVGPU_PMU_PSTATE)) {
113 gk20a_deinit_pstate_support(g);
114 }
115
116 gk20a_mask_interrupts(g);
117
118 g->power_on = false;
119
120 return ret;
121}
122
123int gk20a_finalize_poweron(struct gk20a *g)
124{
125 int err = 0;
126#if defined(CONFIG_TEGRA_GK20A_NVHOST)
127 u32 nr_pages;
128#endif
129
130 u32 fuse_status;
131
132 nvgpu_log_fn(g, " ");
133
134 if (g->power_on) {
135 return 0;
136 }
137
138 g->power_on = true;
139
140 /*
141 * Before probing the GPU make sure the GPU's state is cleared. This is
142 * relevant for rebind operations.
143 */
144 if (g->ops.xve.reset_gpu && !g->gpu_reset_done) {
145 g->ops.xve.reset_gpu(g);
146 g->gpu_reset_done = true;
147 }
148
149 if (g->ops.clock_gating.slcg_acb_load_gating_prod != NULL) {
150 g->ops.clock_gating.slcg_acb_load_gating_prod(g, true);
151 }
152
153 /*
154 * Do this early so any early VMs that get made are capable of mapping
155 * buffers.
156 */
157 err = nvgpu_pd_cache_init(g);
158 if (err) {
159 return err;
160 }
161
162 /* init interface layer support for PMU falcon */
163 err = nvgpu_flcn_sw_init(g, FALCON_ID_PMU);
164 if (err != 0) {
165 nvgpu_err(g, "failed to sw init FALCON_ID_PMU");
166 goto done;
167 }
168 err = nvgpu_flcn_sw_init(g, FALCON_ID_SEC2);
169 if (err != 0) {
170 nvgpu_err(g, "failed to sw init FALCON_ID_SEC2");
171 goto done;
172 }
173 err = nvgpu_flcn_sw_init(g, FALCON_ID_NVDEC);
174 if (err != 0) {
175 nvgpu_err(g, "failed to sw init FALCON_ID_NVDEC");
176 goto done;
177 }
178 err = nvgpu_flcn_sw_init(g, FALCON_ID_GSPLITE);
179 if (err != 0) {
180 nvgpu_err(g, "failed to sw init FALCON_ID_GSPLITE");
181 goto done;
182 }
183
184 if (g->ops.acr.acr_sw_init != NULL &&
185 nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
186 g->ops.acr.acr_sw_init(g, &g->acr);
187 }
188
189 if (g->ops.bios.init) {
190 err = g->ops.bios.init(g);
191 }
192 if (err) {
193 goto done;
194 }
195
196 g->ops.bus.init_hw(g);
197
198 if (g->ops.clk.disable_slowboot) {
199 g->ops.clk.disable_slowboot(g);
200 }
201
202 g->ops.priv_ring.enable_priv_ring(g);
203
204 /* TBD: move this after graphics init in which blcg/slcg is enabled.
205 This function removes SlowdownOnBoot which applies 32x divider
206 on gpcpll bypass path. The purpose of slowdown is to save power
207 during boot but it also significantly slows down gk20a init on
208 simulation and emulation. We should remove SOB after graphics power
209 saving features (blcg/slcg) are enabled. For now, do it here. */
210 if (g->ops.clk.init_clk_support) {
211 err = g->ops.clk.init_clk_support(g);
212 if (err) {
213 nvgpu_err(g, "failed to init gk20a clk");
214 goto done;
215 }
216 }
217
218 if (nvgpu_is_enabled(g, NVGPU_SUPPORT_NVLINK)) {
219 err = g->ops.nvlink.init(g);
220 if (err) {
221 nvgpu_err(g, "failed to init nvlink");
222 goto done;
223 }
224 }
225
226 if (g->ops.fb.init_fbpa) {
227 err = g->ops.fb.init_fbpa(g);
228 if (err) {
229 nvgpu_err(g, "failed to init fbpa");