1 files changed, 759 insertions, 0 deletions

diff --git a/include/gk20a/flcn_gk20a.c b/include/gk20a/flcn_gk20a.c
new file mode 100644
index 0000000..fdcaef9
--- /dev/null
+++ b/include/gk20a/flcn_gk20a.c
@@ -0,0 +1,759 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#include <nvgpu/falcon.h>
+#include <nvgpu/pmu.h>
+#include <nvgpu/io.h>
+
+#include "gk20a/gk20a.h"
+#include "gk20a/flcn_gk20a.h"
+
+#include <nvgpu/hw/gm20b/hw_falcon_gm20b.h>
+
+static int gk20a_flcn_reset(struct nvgpu_falcon *flcn)
+{
+        struct gk20a *g = flcn->g;
+        u32 base_addr = flcn->flcn_base;
+        u32 unit_status = 0;
+        int status = 0;
+
+        if (flcn->flcn_engine_dep_ops.reset_eng) {
+                /* falcon & engine reset */
+                status = flcn->flcn_engine_dep_ops.reset_eng(g);
+        } else {
+                /* do falcon CPU hard reset */
+                unit_status = gk20a_readl(g, base_addr +
+                                falcon_falcon_cpuctl_r());
+                gk20a_writel(g, base_addr + falcon_falcon_cpuctl_r(),
+                        (unit_status | falcon_falcon_cpuctl_hreset_f(1)));
+        }
+
+        return status;
+}
+
+static bool gk20a_flcn_clear_halt_interrupt_status(struct nvgpu_falcon *flcn)
+{
+        struct gk20a *g = flcn->g;
+        u32 base_addr = flcn->flcn_base;
+        u32 data = 0;
+        bool status = false;
+
+        gk20a_writel(g, base_addr + falcon_falcon_irqsclr_r(),
+                gk20a_readl(g, base_addr + falcon_falcon_irqsclr_r()) |
+                (0x10));
+        data = gk20a_readl(g, (base_addr + falcon_falcon_irqstat_r()));
+
+        if ((data & falcon_falcon_irqstat_halt_true_f()) !=
+                falcon_falcon_irqstat_halt_true_f()) {
+                /*halt irq is clear*/
+                status = true;
+        }
+
+        return status;
+}
+
+static void gk20a_flcn_set_irq(struct nvgpu_falcon *flcn, bool enable)
+{
+        struct gk20a *g = flcn->g;
+        u32 base_addr = flcn->flcn_base;
+
+        if (!flcn->is_interrupt_enabled) {
+                nvgpu_warn(g, "Interrupt not supported on flcn 0x%x ",
+                        flcn->flcn_id);
+                /* Keep interrupt disabled */
+                enable = false;
+        }
+
+        if (enable) {
+                gk20a_writel(g, base_addr + falcon_falcon_irqmset_r(),
+                        flcn->intr_mask);
+                gk20a_writel(g, base_addr + falcon_falcon_irqdest_r(),
+                        flcn->intr_dest);
+        } else {
+                gk20a_writel(g, base_addr + falcon_falcon_irqmclr_r(),
+                        0xffffffff);
+        }
+}
+
+static bool gk20a_is_falcon_cpu_halted(struct nvgpu_falcon *flcn)
+{
+        struct gk20a *g = flcn->g;
+        u32 base_addr = flcn->flcn_base;
+
+        return (gk20a_readl(g, base_addr + falcon_falcon_cpuctl_r()) &
+                        falcon_falcon_cpuctl_halt_intr_m() ?
+                        true : false);
+}
+
+static bool gk20a_is_falcon_idle(struct nvgpu_falcon *flcn)
+{
+        struct gk20a *g = flcn->g;
+        u32 base_addr = flcn->flcn_base;
+        u32 unit_status = 0;
+        bool status = false;
+
+        unit_status = gk20a_readl(g,
+                base_addr + falcon_falcon_idlestate_r());
+
+        if (falcon_falcon_idlestate_falcon_busy_v(unit_status) == 0 &&
+                falcon_falcon_idlestate_ext_busy_v(unit_status) == 0) {
+                status = true;
+        } else {
+                status = false;
+        }
+
+        return status;
+}
+
+static bool gk20a_is_falcon_scrubbing_done(struct nvgpu_falcon *flcn)
+{
+        struct gk20a *g = flcn->g;
+        u32 base_addr = flcn->flcn_base;
+        u32 unit_status = 0;
+        bool status = false;
+
+        unit_status = gk20a_readl(g,
+                base_addr + falcon_falcon_dmactl_r());
+
+        if (unit_status & (falcon_falcon_dmactl_dmem_scrubbing_m() |
+                 falcon_falcon_dmactl_imem_scrubbing_m())) {
+                status = false;
+        } else {
+                status = true;
+        }
+
+        return status;
+}
+
+static u32 gk20a_falcon_get_mem_size(struct nvgpu_falcon *flcn,
+                enum flcn_mem_type mem_type)
+{
+        struct gk20a *g = flcn->g;
+        u32 mem_size = 0;
+        u32 hw_cfg_reg = gk20a_readl(g,
+                flcn->flcn_base + falcon_falcon_hwcfg_r());
+
+        if (mem_type == MEM_DMEM) {
+                mem_size = falcon_falcon_hwcfg_dmem_size_v(hw_cfg_reg)
+                        << GK20A_PMU_DMEM_BLKSIZE2;
+        } else {
+                mem_size = falcon_falcon_hwcfg_imem_size_v(hw_cfg_reg)
+                        << GK20A_PMU_DMEM_BLKSIZE2;
+        }
+
+        return mem_size;
+}
+
+static int flcn_mem_overflow_check(struct nvgpu_falcon *flcn,
+                u32 offset, u32 size, enum flcn_mem_type mem_type)
+{
+        struct gk20a *g = flcn->g;
+        u32 mem_size = 0;
+
+        if (size == 0) {
+                nvgpu_err(g, "size is zero");
+                return -EINVAL;
+        }
+
+        if (offset & 0x3) {
+                nvgpu_err(g, "offset (0x%08x) not 4-byte aligned", offset);
+                return -EINVAL;
+        }
+
+        mem_size = gk20a_falcon_get_mem_size(flcn, mem_type);
+        if (!(offset <= mem_size && (offset + size) <= mem_size)) {
+                nvgpu_err(g, "flcn-id 0x%x, copy overflow ",
+                        flcn->flcn_id);
+                nvgpu_err(g, "total size 0x%x, offset 0x%x, copy size 0x%x",
+                        mem_size, offset, size);
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int gk20a_flcn_copy_from_dmem(struct nvgpu_falcon *flcn,
+                u32 src, u8 *dst, u32 size, u8 port)
+{
+        struct gk20a *g = flcn->g;
+        u32 base_addr = flcn->flcn_base;
+        u32 i, words, bytes;
+        u32 data, addr_mask;
+        u32 *dst_u32 = (u32 *)dst;
+
+        nvgpu_log_fn(g, " src dmem offset - %x, size - %x", src, size);
+
+        if (flcn_mem_overflow_check(flcn, src, size, MEM_DMEM)) {
+                nvgpu_err(g, "incorrect parameters");
+                return -EINVAL;
+        }
+
+        nvgpu_mutex_acquire(&flcn->copy_lock);
+
+        words = size >> 2;
+        bytes = size & 0x3;
+
+        addr_mask = falcon_falcon_dmemc_offs_m() |
+                            falcon_falcon_dmemc_blk_m();
+
+        src &= addr_mask;
+
+        gk20a_writel(g, base_addr + falcon_falcon_dmemc_r(port),
+                src | falcon_falcon_dmemc_aincr_f(1));
+
+        for (i = 0; i < words; i++) {
+                dst_u32[i] = gk20a_readl(g,
+                        base_addr + falcon_falcon_dmemd_r(port));