1 files changed, 23 insertions, 31 deletions

diff --git a/include/gk20a/fifo_gk20a.c b/include/gk20a/fifo_gk20a.c
index 4477f7c..77babc7 100644
--- a/include/gk20a/fifo_gk20a.c
+++ b/include/gk20a/fifo_gk20a.c
@@ -1,7 +1,7 @@
 /*
  * GK20A Graphics FIFO (gr host)
  *
- * Copyright (c) 2011-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -58,8 +58,6 @@
 #include <nvgpu/hw/gk20a/hw_top_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_gr_gk20a.h>
 
-#include <os/linux/os_linux.h>
-
 #define FECS_METHOD_WFI_RESTORE 0x80000
 #define FECS_MAILBOX_0_ACK_RESTORE 0x4
 
@@ -1409,6 +1407,7 @@ static void gk20a_fifo_handle_chsw_fault(struct gk20a *g)
         intr = gk20a_readl(g, fifo_intr_chsw_error_r());
         nvgpu_err(g, "chsw: %08x", intr);
         gk20a_fecs_dump_falcon_stats(g);
+        gk20a_gpccs_dump_falcon_stats(g);
         gk20a_writel(g, fifo_intr_chsw_error_r(), intr);
 }
 
@@ -1604,6 +1603,7 @@ int gk20a_fifo_deferred_reset(struct gk20a *g, struct channel_gk20a *ch)
                 engines = gk20a_fifo_engines_on_id(g, tsg->tsgid, true);
         } else {
                 nvgpu_err(g, "chid: %d is not bound to tsg", ch->chid);
+                engines = g->fifo.deferred_fault_engines;
         }
 
         if (engines == 0U) {
@@ -1724,6 +1724,7 @@ static bool gk20a_fifo_handle_mmu_fault_locked(
 
                 if (ctxsw) {
                         gk20a_fecs_dump_falcon_stats(g);
+                        gk20a_gpccs_dump_falcon_stats(g);
                         nvgpu_err(g, "gr_status_r : 0x%x",
                                         gk20a_readl(g, gr_status_r()));
                 }
@@ -2198,9 +2199,9 @@ int gk20a_fifo_tsg_unbind_channel_verify_status(struct channel_gk20a *ch)
         struct gk20a *g = ch->g;
 
         if (gk20a_fifo_channel_status_is_next(g, ch->chid)) {
-                nvgpu_err(g, "Channel %d to be removed from TSG %d has NEXT set!",
+                nvgpu_log_info(g, "Channel %d to be removed from TSG %d has NEXT set!",
                         ch->chid, ch->tsgid);
-                return -EINVAL;
+                return -EAGAIN;
         }
 
         if (g->ops.fifo.tsg_verify_status_ctx_reload) {
@@ -2983,7 +2984,7 @@ static u32 gk20a_fifo_get_preempt_timeout(struct gk20a *g)
 }
 
 int gk20a_fifo_is_preempt_pending(struct gk20a *g, u32 id,
-                unsigned int id_type)
+                unsigned int id_type, bool preempt_retries_left)
 {
         struct nvgpu_timeout timeout;
         u32 delay = GR_IDLE_CHECK_DEFAULT;
@@ -3039,7 +3040,8 @@ void gk20a_fifo_preempt_timeout_rc(struct gk20a *g, struct channel_gk20a *ch)
                                         RC_TYPE_PREEMPT_TIMEOUT);
 }
 
-int __locked_fifo_preempt(struct gk20a *g, u32 id, bool is_tsg)
+int __locked_fifo_preempt(struct gk20a *g, u32 id, bool is_tsg,
+                          bool preempt_retries_left)
 {
         int ret;
         unsigned int id_type;
@@ -3051,8 +3053,17 @@ int __locked_fifo_preempt(struct gk20a *g, u32 id, bool is_tsg)
 
         id_type = is_tsg ? ID_TYPE_TSG : ID_TYPE_CHANNEL;
 
-        /* wait for preempt */
-        ret = g->ops.fifo.is_preempt_pending(g, id, id_type);
+        /*
+         * Poll for preempt done. if stalling interrupts are pending
+         * while preempt is in progress we poll for stalling interrupts
+         * to finish based on return value from this function and
+         * retry preempt again.
+         * If HW is hung, on the last retry instance we try to identify
+         * the engines hung and set the runlist reset_eng_bitmask
+         * and mark preemption completion.
+         */
+        ret = g->ops.fifo.is_preempt_pending(g, id, id_type,
+                                             preempt_retries_left);
 
         return ret;
 }
@@ -3074,7 +3085,7 @@ int gk20a_fifo_preempt_channel(struct gk20a *g, struct channel_gk20a *ch)
 
         mutex_ret = nvgpu_pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token);
 
-        ret = __locked_fifo_preempt(g, ch->chid, false);
+        ret = __locked_fifo_preempt(g, ch->chid, false, false);
 
         if (!mutex_ret) {
                 nvgpu_pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token);
@@ -3114,7 +3125,7 @@ int gk20a_fifo_preempt_tsg(struct gk20a *g, struct tsg_gk20a *tsg)
 
         mutex_ret = nvgpu_pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token);
 
-        ret = __locked_fifo_preempt(g, tsg->tsgid, true);
+        ret = __locked_fifo_preempt(g, tsg->tsgid, true, false);
 
         if (!mutex_ret) {
                 nvgpu_pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token);
@@ -3584,36 +3595,17 @@ void gk20a_fifo_runlist_hw_submit(struct gk20a *g, u32 runlist_id,
 {
         struct fifo_runlist_info_gk20a *runlist = NULL;
         u64 runlist_iova;
-        u32 val_wrote;
-        struct nvgpu_os_linux *l;
 
         runlist = &g->fifo.runlist_info[runlist_id];
         runlist_iova = nvgpu_mem_get_addr(g, &runlist->mem[buffer_index]);
 
-
         if (count != 0) {
-                printk(KERN_INFO "Runlist base register: %0x\n", fifo_runlist_base_r());
-                printk(KERN_INFO "Runlist KVA:  %px\n", (void*)(runlist->mem[buffer_index].cpu_va));
-                printk(KERN_INFO "Runlist PA:   %px\n", (void*)virt_to_phys((runlist->mem[buffer_index].cpu_va)));
-                printk(KERN_INFO "Runlist dma_address:  %px\n", (void*)(runlist->mem[buffer_index].priv.sgt->sgl->dma_address));
-                printk(KERN_INFO "Runlist pages KVA:  %px\n", (void*)(runlist->mem[buffer_index].priv.pages));
-                printk(KERN_INFO "Runlist pages PA:   %px\n", (void*)virt_to_phys(runlist->mem[buffer_index].priv.pages));
-                printk(KERN_INFO "Runlist dma_address:  %px\n", (void*)(runlist->mem[buffer_index].priv.sgt->sgl->dma_address));
-                printk(KERN_INFO "Runlist page_to_phys %px + offset %px\n", (void*)(page_to_phys(sg_page(runlist->mem[buffer_index].priv.sgt->sgl))), (void*)(runlist->mem[buffer_index].priv.sgt->sgl->offset));
-                printk(KERN_INFO "Runlist IOVA: %px\n", (void*)runlist_iova);
-                printk(KERN_INFO "Using struct gk20* %px\n", g);
-                printk(KERN_INFO "g->name: %s, g->power_on: %d, g->sw_ready: %d, g->is_virtual %d\n", g->name, g->power_on, g->sw_ready, g->is_virtual);
-                printk(KERN_INFO "COHERENT_SYSMEM? %d, iommuable? %d\n", nvgpu_is_enabled(g, NVGPU_USE_COHERENT_SYSMEM), nvgpu_iommuable(g));
-                l = container_of(g, struct nvgpu_os_linux, g);
-                printk(KERN_INFO "l->regs %px\n", l->regs);
                 gk20a_writel(g, fifo_runlist_base_r(),
                         fifo_runlist_base_ptr_f(u64_lo32(runlist_iova >> 12)) |
                         nvgpu_aperture_mask(g, &runlist->mem[buffer_index],
                                 fifo_runlist_base_target_sys_mem_ncoh_f(),
                                 fifo_runlist_base_target_sys_mem_coh_f(),
                                 fifo_runlist_base_target_vid_mem_f()));
-                val_wrote = nvgpu_readl(g, 0x2270);
-                printk(KERN_INFO "Wrote runlist base as %0llx\n", (u64)(val_wrote & 0x0fffffff) << 12);
         }
 
         gk20a_writel(g, fifo_runlist_r(),
@@ -3806,7 +3798,7 @@ static int __locked_fifo_reschedule_preempt_next(struct channel_gk20a *ch,
                 gk20a_readl(g, fifo_preempt_r()));
 #endif
         if (wait_preempt) {
-                g->ops.fifo.is_preempt_pending(g, preempt_id, preempt_type);
+                g->ops.fifo.is_preempt_pending(g, preempt_id, preempt_type, false);
         }
 #ifdef TRACEPOINTS_ENABLED
         trace_gk20a_reschedule_preempted_next(ch->chid);