1 files changed, 0 insertions, 134 deletions
diff --git a/include/gk20a/clk_gk20a.h b/include/gk20a/clk_gk20a.h
deleted file mode 100644
index b8ec942..0000000
--- a/include/gk20a/clk_gk20a.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * Copyright (c) 2011 - 2019, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-#ifndef CLK_GK20A_H
-#define CLK_GK20A_H
-#include <nvgpu/lock.h>
-#if defined(CONFIG_COMMON_CLK)
-#include <linux/clk-provider.h>
-#endif
-#define GPUFREQ_TABLE_END     ~(u32)1
-enum {
-        /* only one PLL for gk20a */
-        GK20A_GPC_PLL = 0,
-        /* 2 PLL revisions for gm20b */
-        GM20B_GPC_PLL_B1,
-        GM20B_GPC_PLL_C1,
-};
-enum gpc_pll_mode {
-        GPC_PLL_MODE_F = 0,     /* fixed frequency mode a.k.a legacy mode */
-        GPC_PLL_MODE_DVFS,      /* DVFS mode a.k.a NA mode */
-};
-struct na_dvfs {
-        u32 n_int;
-        u32 sdm_din;
-        int dfs_coeff;
-        int dfs_det_max;
-        int dfs_ext_cal;
-        int uv_cal;
-        int mv;
-};
-struct pll {
-        u32 id;
-        u32 clk_in;     /* KHz */
-        u32 M;
-        u32 N;
-        u32 PL;
-        u32 freq;       /* KHz */
-        bool enabled;
-        enum gpc_pll_mode mode;
-        struct na_dvfs dvfs;
-};
-struct pll_parms {
-        u32 min_freq, max_freq; /* KHz */
-        u32 min_vco, max_vco;   /* KHz */
-        u32 min_u,   max_u;     /* KHz */
-        u32 min_M,   max_M;
-        u32 min_N,   max_N;
-        u32 min_PL,  max_PL;
-        /* NA mode parameters*/
-        int coeff_slope, coeff_offs; /* coeff = slope * V + offs */
-        int uvdet_slope, uvdet_offs; /* uV = slope * det + offs */
-        u32 vco_ctrl;
-        /*
-         * Timing parameters in us. Lock timeout is applied to locking in fixed
-         * frequency mode and to dynamic ramp in any mode; does not affect lock
-         * latency, since lock/ramp done status bit is polled. NA mode lock and
-         * and IDDQ exit delays set the time of the respective opertaions with
-         * no status polling.
-         */
-        u32 lock_timeout;
-        u32 na_lock_delay;
-        u32 iddq_exit_delay;
-        /* NA mode DFS control */
-        u32 dfs_ctrl;
-};
-struct namemap_cfg;
-struct clk_gk20a {
-        struct gk20a *g;
-#if defined(CONFIG_COMMON_CLK)
-        struct clk *tegra_clk;
-        struct clk *tegra_clk_parent;
-        struct clk_hw hw;
-#endif
-        struct pll gpc_pll;
-        struct pll gpc_pll_last;
-        struct nvgpu_mutex clk_mutex;
-        struct namemap_cfg *clk_namemap;
-        u32 namemap_num;
-        u32 *namemap_xlat_table;
-        bool sw_ready;
-        bool clk_hw_on;
-        bool debugfs_set;
-        int pll_poweron_uv;
-        unsigned long dvfs_safe_max_freq;
-};
-#if defined(CONFIG_COMMON_CLK)
-#define to_clk_gk20a(_hw) container_of(_hw, struct clk_gk20a, hw)
-#endif
-struct gpu_ops;
-#define KHZ 1000
-#define MHZ 1000000
-static inline unsigned long rate_gpc2clk_to_gpu(unsigned long rate)
-{
-        /* convert the kHz gpc2clk frequency to Hz gpcpll frequency */
-        return (rate * KHZ) / 2;
-}
-static inline unsigned long rate_gpu_to_gpc2clk(unsigned long rate)
-{
-        /* convert the Hz gpcpll frequency to kHz gpc2clk frequency */
-        return (rate * 2) / KHZ;
-}
-#endif /* CLK_GK20A_H */

diff --git a/include/gk20a/clk_gk20a.h b/include/gk20a/clk_gk20a.h deleted file mode 100644 index b8ec942..0000000 --- a/include/gk20a/clk_gk20a.h +++ /dev/null
@@ -1,134 +0,0 @@
1	/*
2	* Copyright (c) 2011 - 2019, NVIDIA CORPORATION. All rights reserved.
3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:
10	*
11	* The above copyright notice and this permission notice shall be included in
12	* all copies or substantial portions of the Software.
13	*
14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20	* DEALINGS IN THE SOFTWARE.
21	*/
22	#ifndef CLK_GK20A_H
23	#define CLK_GK20A_H
24
25	#include <nvgpu/lock.h>
26
27	#if defined(CONFIG_COMMON_CLK)
28	#include <linux/clk-provider.h>
29	#endif
30
31	#define GPUFREQ_TABLE_END ~(u32)1
32	enum {
33	/* only one PLL for gk20a */
34	GK20A_GPC_PLL = 0,
35	/* 2 PLL revisions for gm20b */
36	GM20B_GPC_PLL_B1,
37	GM20B_GPC_PLL_C1,
38	};
39
40	enum gpc_pll_mode {
41	GPC_PLL_MODE_F = 0, /* fixed frequency mode a.k.a legacy mode */
42	GPC_PLL_MODE_DVFS, /* DVFS mode a.k.a NA mode */
43	};
44
45	struct na_dvfs {
46	u32 n_int;
47	u32 sdm_din;
48	int dfs_coeff;
49	int dfs_det_max;
50	int dfs_ext_cal;
51	int uv_cal;
52	int mv;
53	};
54
55	struct pll {
56	u32 id;
57	u32 clk_in; /* KHz */
58	u32 M;
59	u32 N;
60	u32 PL;
61	u32 freq; /* KHz */
62	bool enabled;
63	enum gpc_pll_mode mode;
64	struct na_dvfs dvfs;
65	};
66
67	struct pll_parms {
68	u32 min_freq, max_freq; /* KHz */
69	u32 min_vco, max_vco; /* KHz */
70	u32 min_u, max_u; /* KHz */
71	u32 min_M, max_M;
72	u32 min_N, max_N;
73	u32 min_PL, max_PL;
74	/* NA mode parameters*/
75	int coeff_slope, coeff_offs; /* coeff = slope * V + offs */
76	int uvdet_slope, uvdet_offs; /* uV = slope * det + offs */
77	u32 vco_ctrl;
78	/*
79	* Timing parameters in us. Lock timeout is applied to locking in fixed
80	* frequency mode and to dynamic ramp in any mode; does not affect lock
81	* latency, since lock/ramp done status bit is polled. NA mode lock and
82	* and IDDQ exit delays set the time of the respective opertaions with
83	* no status polling.
84	*/
85	u32 lock_timeout;
86	u32 na_lock_delay;
87	u32 iddq_exit_delay;
88	/* NA mode DFS control */
89	u32 dfs_ctrl;
90	};
91
92	struct namemap_cfg;
93
94	struct clk_gk20a {
95	struct gk20a *g;
96	#if defined(CONFIG_COMMON_CLK)
97	struct clk *tegra_clk;
98	struct clk *tegra_clk_parent;
99	struct clk_hw hw;
100	#endif
101	struct pll gpc_pll;
102	struct pll gpc_pll_last;
103	struct nvgpu_mutex clk_mutex;
104	struct namemap_cfg *clk_namemap;
105	u32 namemap_num;
106	u32 *namemap_xlat_table;
107	bool sw_ready;
108	bool clk_hw_on;
109	bool debugfs_set;
110	int pll_poweron_uv;
111	unsigned long dvfs_safe_max_freq;
112	};
113
114	#if defined(CONFIG_COMMON_CLK)
115	#define to_clk_gk20a(_hw) container_of(_hw, struct clk_gk20a, hw)
116	#endif
117
118	struct gpu_ops;
119
120	#define KHZ 1000
121	#define MHZ 1000000
122
123	static inline unsigned long rate_gpc2clk_to_gpu(unsigned long rate)
124	{
125	/* convert the kHz gpc2clk frequency to Hz gpcpll frequency */
126	return (rate * KHZ) / 2;
127	}
128	static inline unsigned long rate_gpu_to_gpc2clk(unsigned long rate)
129	{
130	/* convert the Hz gpcpll frequency to kHz gpc2clk frequency */
131	return (rate * 2) / KHZ;
132	}
133
134	#endif /* CLK_GK20A_H */