1 files changed, 576 insertions, 0 deletions

diff --git a/include/gk20a/ce2_gk20a.c b/include/gk20a/ce2_gk20a.c
new file mode 100644
index 0000000..2a40b08
--- /dev/null
+++ b/include/gk20a/ce2_gk20a.c
@@ -0,0 +1,576 @@
+/*
+ * GK20A Graphics Copy Engine  (gr host)
+ *
+ * Copyright (c) 2011-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/kmem.h>
+#include <nvgpu/dma.h>
+#include <nvgpu/os_sched.h>
+#include <nvgpu/log.h>
+#include <nvgpu/enabled.h>
+#include <nvgpu/io.h>
+#include <nvgpu/utils.h>
+#include <nvgpu/channel.h>
+#include <nvgpu/power_features/cg.h>
+
+#include "gk20a.h"
+#include "gk20a/fence_gk20a.h"
+
+#include <nvgpu/hw/gk20a/hw_ce2_gk20a.h>
+#include <nvgpu/hw/gk20a/hw_pbdma_gk20a.h>
+#include <nvgpu/hw/gk20a/hw_ccsr_gk20a.h>
+#include <nvgpu/hw/gk20a/hw_ram_gk20a.h>
+#include <nvgpu/hw/gk20a/hw_top_gk20a.h>
+#include <nvgpu/hw/gk20a/hw_gr_gk20a.h>
+#include <nvgpu/barrier.h>
+
+/*
+ * Copy engine defines line size in pixels
+ */
+#define MAX_CE_SHIFT    31      /* 4Gpixels -1 */
+#define MAX_CE_MASK     ((u32) (~(~0U << MAX_CE_SHIFT)))
+#define MAX_CE_ALIGN(a) (a & MAX_CE_MASK)
+
+
+static u32 ce2_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr)
+{
+        nvgpu_log(g, gpu_dbg_intr, "ce2 non-blocking pipe interrupt\n");
+
+        return ce2_intr_status_nonblockpipe_pending_f();
+}
+
+static u32 ce2_blockpipe_isr(struct gk20a *g, u32 fifo_intr)
+{
+        nvgpu_log(g, gpu_dbg_intr, "ce2 blocking pipe interrupt\n");
+
+        return ce2_intr_status_blockpipe_pending_f();
+}
+
+static u32 ce2_launcherr_isr(struct gk20a *g, u32 fifo_intr)
+{
+        nvgpu_log(g, gpu_dbg_intr, "ce2 launch error interrupt\n");
+
+        return ce2_intr_status_launcherr_pending_f();
+}
+
+void gk20a_ce2_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
+{
+        u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r());
+        u32 clear_intr = 0;
+
+        nvgpu_log(g, gpu_dbg_intr, "ce2 isr %08x\n", ce2_intr);
+
+        /* clear blocking interrupts: they exibit broken behavior */
+        if (ce2_intr & ce2_intr_status_blockpipe_pending_f()) {
+                clear_intr |= ce2_blockpipe_isr(g, ce2_intr);
+        }
+
+        if (ce2_intr & ce2_intr_status_launcherr_pending_f()) {
+                clear_intr |= ce2_launcherr_isr(g, ce2_intr);
+        }
+
+        gk20a_writel(g, ce2_intr_status_r(), clear_intr);
+        return;
+}
+
+u32 gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
+{
+        u32 ops = 0;
+        u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r());
+
+        nvgpu_log(g, gpu_dbg_intr, "ce2 nonstall isr %08x\n", ce2_intr);
+
+        if (ce2_intr & ce2_intr_status_nonblockpipe_pending_f()) {
+                gk20a_writel(g, ce2_intr_status_r(),
+                        ce2_nonblockpipe_isr(g, ce2_intr));
+                ops |= (GK20A_NONSTALL_OPS_WAKEUP_SEMAPHORE |
+                        GK20A_NONSTALL_OPS_POST_EVENTS);
+        }
+        return ops;
+}
+
+/* static CE app api */
+static void gk20a_ce_put_fences(struct gk20a_gpu_ctx *ce_ctx)
+{
+        u32 i;
+
+        for (i = 0; i < NVGPU_CE_MAX_INFLIGHT_JOBS; i++) {
+                struct gk20a_fence **fence = &ce_ctx->postfences[i];
+                if (*fence) {
+                        gk20a_fence_put(*fence);
+                }
+                *fence = NULL;
+        }
+}
+
+/* assume this api should need to call under nvgpu_mutex_acquire(&ce_app->app_mutex) */
+static void gk20a_ce_delete_gpu_context(struct gk20a_gpu_ctx *ce_ctx)
+{
+        struct nvgpu_list_node *list = &ce_ctx->list;
+
+        ce_ctx->gpu_ctx_state = NVGPU_CE_GPU_CTX_DELETED;
+
+        nvgpu_mutex_acquire(&ce_ctx->gpu_ctx_mutex);
+
+        if (nvgpu_mem_is_valid(&ce_ctx->cmd_buf_mem)) {
+                gk20a_ce_put_fences(ce_ctx);
+                nvgpu_dma_unmap_free(ce_ctx->vm, &ce_ctx->cmd_buf_mem);
+        }
+
+        /*
+         * free the channel
+         * gk20a_channel_close() will also unbind the channel from TSG
+         */
+        gk20a_channel_close(ce_ctx->ch);
+        nvgpu_ref_put(&ce_ctx->tsg->refcount, gk20a_tsg_release);
+
+        /* housekeeping on app */
+        if (list->prev && list->next) {
+                nvgpu_list_del(list);
+        }
+
+        nvgpu_mutex_release(&ce_ctx->gpu_ctx_mutex);
+        nvgpu_mutex_destroy(&ce_ctx->gpu_ctx_mutex);
+
+        nvgpu_kfree(ce_ctx->g, ce_ctx);
+}
+
+static inline unsigned int gk20a_ce_get_method_size(int request_operation,
+                        u64 size)
+{
+        /* failure size */
+        unsigned int methodsize = UINT_MAX;
+        unsigned int iterations = 0;
+        u32 shift;
+        u64 chunk = size;
+        u32 height, width;
+
+        while (chunk) {
+                iterations++;
+
+                shift = MAX_CE_ALIGN(chunk) ? __ffs(MAX_CE_ALIGN(chunk)) :
+                                                MAX_CE_SHIFT;
+                width = chunk >> shift;
+                height = 1 << shift;
+                width = MAX_CE_ALIGN(width);
+
+                chunk -= (u64) height * width;
+        }
+
+        if (request_operation & NVGPU_CE_PHYS_MODE_TRANSFER) {
+                methodsize = (2 + (16 * iterations)) * sizeof(u32);
+        } else if (request_operation & NVGPU_CE_MEMSET) {
+                methodsize = (2 + (15 * iterations)) * sizeof(u32);
+        }
+
+        return methodsize;
+}
+
+int gk20a_ce_prepare_submit(u64 src_buf,
+                u64 dst_buf,
+                u64 size,
+                u32 *cmd_buf_cpu_va,
+                u32 max_cmd_buf_size,
+                unsigned int payload,
+                int launch_flags,
+                int request_operation,
+                u32 dma_copy_class)
+{
+        u32 launch = 0;
+        u32 methodSize = 0;
+        u64 offset = 0;
+        u64 chunk_size = 0;
+        u64 chunk = size;
+
+        /* failure case handling */
+        if ((gk20a_ce_get_method_size(request_operation, size) >
+                max_cmd_buf_size) || (!size) ||
+                (request_operation > NVGPU_CE_MEMSET)) {
+                return 0;
+        }
+
+        /* set the channel object */
+        cmd_buf_cpu_va[methodSize++] = 0x20018000;
+        cmd_buf_cpu_va[methodSize++] = dma_copy_class;
+
+        /*
+         * The purpose clear the memory in 2D rectangles. We get the ffs to
+         * determine the number of lines to copy. The only constraint is that
+         * maximum number of pixels per line is 4Gpix - 1, which is awkward for
+         * calculation, so we settle to 2Gpix per line to make calculatione
+         * more agreable
+         */
+
+        /* The copy engine in 2D mode can have (2^32 - 1) x (2^32 - 1) pixels in
+         * a single submit, we are going to try to clear a range of up to 2Gpix
+         * multiple lines.