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-rw-r--r--include/ctrl/ctrlvolt.h143
1 files changed, 0 insertions, 143 deletions
diff --git a/include/ctrl/ctrlvolt.h b/include/ctrl/ctrlvolt.h
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--- a/include/ctrl/ctrlvolt.h
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1/*
2 * general p state infrastructure
3 *
4 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24#ifndef NVGPU_CTRLVOLT_H
25#define NVGPU_CTRLVOLT_H
26
27#define CTRL_VOLT_VOLT_RAIL_MAX_RAILS \
28 CTRL_BOARDOBJGRP_E32_MAX_OBJECTS
29
30#include "ctrlperf.h"
31#include "ctrlboardobj.h"
32
33#define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES 0x04U
34#define CTRL_VOLT_VOLT_DEV_VID_VSEL_MAX_ENTRIES (8U)
35#define CTRL_VOLT_DOMAIN_INVALID 0x00U
36#define CTRL_VOLT_DOMAIN_LOGIC 0x01U
37#define CLK_PROG_VFE_ENTRY_LOGIC 0x00U
38#define CLK_PROG_VFE_ENTRY_SRAM 0x01U
39
40/*
41 * Macros for Voltage Domain HAL.
42 */
43#define CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL 0x00U
44#define CTRL_VOLT_DOMAIN_HAL_GP10X_SPLIT_RAIL 0x01U
45
46/*
47 * Macros for Voltage Domains.
48 */
49#define CTRL_VOLT_DOMAIN_INVALID 0x00U
50#define CTRL_VOLT_DOMAIN_LOGIC 0x01U
51#define CTRL_VOLT_DOMAIN_SRAM 0x02U
52
53/*!
54 * Special value corresponding to an invalid Voltage Rail Index.
55 */
56#define CTRL_VOLT_RAIL_INDEX_INVALID \
57 CTRL_BOARDOBJ_IDX_INVALID
58
59/*!
60 * Special value corresponding to an invalid Voltage Device Index.
61 */
62#define CTRL_VOLT_DEVICE_INDEX_INVALID \
63 CTRL_BOARDOBJ_IDX_INVALID
64
65/*!
66 * Special value corresponding to an invalid Voltage Policy Index.
67 */
68#define CTRL_VOLT_POLICY_INDEX_INVALID \
69 CTRL_BOARDOBJ_IDX_INVALID
70
71enum nv_pmu_pmgr_pwm_source {
72 NV_PMU_PMGR_PWM_SOURCE_INVALID = 0,
73 NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_0 = 4,
74 NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_1,
75 NV_PMU_PMGR_PWM_SOURCE_RSVD_0 = 7,
76 NV_PMU_PMGR_PWM_SOURCE_RSVD_1 = 8,
77};
78
79/*!
80 * Macros for Voltage Device Types.
81 */
82#define CTRL_VOLT_DEVICE_TYPE_INVALID 0x00U
83#define CTRL_VOLT_DEVICE_TYPE_PWM 0x03U
84
85/*
86 * Macros for Volt Device Operation types.
87 */
88#define CTRL_VOLT_DEVICE_OPERATION_TYPE_INVALID 0x00U
89#define CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT 0x01U
90#define CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_STEADY_STATE 0x02U
91#define CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_SLEEP_STATE 0x03U
92#define CTRL_VOLT_VOLT_DEVICE_OPERATION_TYPE_IPC_VMIN 0x04U
93
94/*!
95 * Macros for Voltage Domains.
96 */
97#define CTRL_VOLT_DOMAIN_INVALID 0x00U
98#define CTRL_VOLT_DOMAIN_LOGIC 0x01U
99#define CTRL_VOLT_DOMAIN_SRAM 0x02U
100
101/*!
102 * Macros for Volt Policy types.
103 *
104 * Virtual VOLT_POLICY types are indexed starting from 0xFF.
105 */
106#define CTRL_VOLT_POLICY_TYPE_INVALID 0x00U
107#define CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL 0x01U
108#define CTRL_VOLT_POLICY_TYPE_SR_MULTI_STEP 0x02U
109#define CTRL_VOLT_POLICY_TYPE_SR_SINGLE_STEP 0x03U
110#define CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL_MULTI_STEP 0x04U
111#define CTRL_VOLT_POLICY_TYPE_SPLIT_RAIL 0xFEU
112#define CTRL_VOLT_POLICY_TYPE_UNKNOWN 0xFFU
113
114/*!
115 * Macros for Volt Policy Client types.
116 */
117#define CTRL_VOLT_POLICY_CLIENT_INVALID 0x00U
118#define CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ 0x01U
119
120struct ctrl_volt_volt_rail_list_item {
121 u8 rail_idx;
122 u32 voltage_uv;
123};
124
125struct ctrl_volt_volt_rail_list {
126 u8 num_rails;
127 struct ctrl_volt_volt_rail_list_item
128 rails[CTRL_VOLT_VOLT_RAIL_MAX_RAILS];
129};
130
131struct ctrl_volt_volt_rail_list_item_v1 {
132 u8 rail_idx;
133 u32 voltage_uv;
134 u32 voltage_min_noise_unaware_uv;
135};
136
137struct ctrl_volt_volt_rail_list_v1 {
138 u8 num_rails;
139 struct ctrl_volt_volt_rail_list_item_v1
140 rails[CTRL_VOLT_VOLT_RAIL_MAX_RAILS];
141};
142
143#endif /* NVGPU_CTRLVOLT_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-30 12:14:14 -0400