diff options
Diffstat (limited to 'include/clk/clk_fll.h')
-rw-r--r-- | include/clk/clk_fll.h | 81 |
1 files changed, 81 insertions, 0 deletions
diff --git a/include/clk/clk_fll.h b/include/clk/clk_fll.h new file mode 100644 index 0000000..6cbdfe2 --- /dev/null +++ b/include/clk/clk_fll.h | |||
@@ -0,0 +1,81 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef NVGPU_CLK_FLL_H | ||
24 | #define NVGPU_CLK_FLL_H | ||
25 | |||
26 | #include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h> | ||
27 | #include "boardobj/boardobjgrp_e32.h" | ||
28 | #include "boardobj/boardobjgrpmask.h" | ||
29 | |||
30 | /*data and function definition to talk to driver*/ | ||
31 | int clk_fll_sw_setup(struct gk20a *g); | ||
32 | int clk_fll_pmu_setup(struct gk20a *g); | ||
33 | |||
34 | struct avfsfllobjs { | ||
35 | struct boardobjgrp_e32 super; | ||
36 | struct boardobjgrpmask_e32 lut_prog_master_mask; | ||
37 | u32 lut_step_size_uv; | ||
38 | u32 lut_min_voltage_uv; | ||
39 | u8 lut_num_entries; | ||
40 | u16 max_min_freq_mhz; | ||
41 | }; | ||
42 | |||
43 | struct fll_device; | ||
44 | |||
45 | typedef u32 fll_lut_broadcast_slave_register(struct gk20a *g, | ||
46 | struct avfsfllobjs *pfllobjs, | ||
47 | struct fll_device *pfll, | ||
48 | struct fll_device *pfll_slave); | ||
49 | |||
50 | struct fll_device { | ||
51 | struct boardobj super; | ||
52 | u8 id; | ||
53 | u8 mdiv; | ||
54 | u16 input_freq_mhz; | ||
55 | u32 clk_domain; | ||
56 | u8 vin_idx_logic; | ||
57 | u8 vin_idx_sram; | ||
58 | u8 rail_idx_for_lut; | ||
59 | struct nv_pmu_clk_lut_device_desc lut_device; | ||
60 | struct nv_pmu_clk_regime_desc regime_desc; | ||
61 | u8 min_freq_vfe_idx; | ||
62 | u8 freq_ctrl_idx; | ||
63 | u8 target_regime_id_override; | ||
64 | bool b_skip_pldiv_below_dvco_min; | ||
65 | bool b_dvco_1x; | ||
66 | struct boardobjgrpmask_e32 lut_prog_broadcast_slave_mask; | ||
67 | fll_lut_broadcast_slave_register *lut_broadcast_slave_register; | ||
68 | }; | ||
69 | |||
70 | u32 nvgpu_clk_get_vbios_clk_domain_gv10x( u32 vbios_domain); | ||
71 | u32 nvgpu_clk_get_vbios_clk_domain_gp10x( u32 vbios_domain); | ||
72 | |||
73 | #define CLK_FLL_LUT_VF_NUM_ENTRIES(pclk) \ | ||
74 | (pclk->avfs_fllobjs.lut_num_entries) | ||
75 | |||
76 | #define CLK_FLL_LUT_MIN_VOLTAGE_UV(pclk) \ | ||
77 | (pclk->avfs_fllobjs.lut_min_voltage_uv) | ||
78 | #define CLK_FLL_LUT_STEP_SIZE_UV(pclk) \ | ||
79 | (pclk->avfs_fllobjs.lut_step_size_uv) | ||
80 | |||
81 | #endif /* NVGPU_CLK_FLL_H */ | ||