aboutsummaryrefslogtreecommitdiffstats
path: root/include/clk/clk.h
diff options
context:
space:
mode:
Diffstat (limited to 'include/clk/clk.h')
-rw-r--r--include/clk/clk.h144
1 files changed, 0 insertions, 144 deletions
diff --git a/include/clk/clk.h b/include/clk/clk.h
deleted file mode 100644
index 3f4bdf7..0000000
--- a/include/clk/clk.h
+++ /dev/null
@@ -1,144 +0,0 @@
1/*
2 * general clock structures & definitions
3 *
4 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24#ifndef NVGPU_CLK_H
25#define NVGPU_CLK_H
26
27#include "clk_vin.h"
28#include "clk_fll.h"
29#include "clk_domain.h"
30#include "clk_prog.h"
31#include "clk_vf_point.h"
32#include "clk_mclk.h"
33#include "clk_freq_controller.h"
34
35#define NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_SKIP 0x10
36#define NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_MASK 0x1F
37#define NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_SHIFT 0
38#define BOOT_GPCCLK_MHZ 952
39
40struct gk20a;
41
42int clk_set_boot_fll_clk(struct gk20a *g);
43
44/* clock related defines for GPUs supporting clock control from pmu*/
45struct clk_pmupstate {
46 struct avfsvinobjs avfs_vinobjs;
47 struct avfsfllobjs avfs_fllobjs;
48 struct clk_domains clk_domainobjs;
49 struct clk_progs clk_progobjs;
50 struct clk_vf_points clk_vf_pointobjs;
51 struct clk_mclk_state clk_mclk;
52 struct clk_freq_controllers clk_freq_controllers;
53};
54
55struct clockentry {
56 u8 vbios_clk_domain;
57 u8 clk_which;
58 u8 perf_index;
59 u32 api_clk_domain;
60};
61
62struct change_fll_clk {
63 u32 api_clk_domain;
64 u16 clkmhz;
65 u32 voltuv;
66};
67
68struct set_fll_clk {
69 u32 voltuv;
70 u16 gpc2clkmhz;
71 u32 current_regime_id_gpc;
72 u32 target_regime_id_gpc;
73 u16 sys2clkmhz;
74 u32 current_regime_id_sys;
75 u32 target_regime_id_sys;
76 u16 xbar2clkmhz;
77 u32 current_regime_id_xbar;
78 u32 target_regime_id_xbar;
79};
80
81#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_MAX_NUMCLKS 9
82
83struct vbios_clock_domain {
84 u8 clock_type;
85 u8 num_domains;
86 struct clockentry clock_entry[NV_PERF_HEADER_4X_CLOCKS_DOMAINS_MAX_NUMCLKS];
87};
88
89struct vbios_clocks_table_1x_hal_clock_entry {
90 enum nv_pmu_clk_clkwhich domain;
91 bool b_noise_aware_capable;
92 u8 clk_vf_curve_count;
93};
94
95#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_GPC2CLK 0
96#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_XBAR2CLK 1
97#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_DRAMCLK 2
98#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_SYS2CLK 3
99#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_HUB2CLK 4
100#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_MSDCLK 5
101#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_PWRCLK 6
102#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_DISPCLK 7
103#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_NUMCLKS 8
104
105#define PERF_CLK_MCLK 0
106#define PERF_CLK_DISPCLK 1
107#define PERF_CLK_GPC2CLK 2
108#define PERF_CLK_HOSTCLK 3
109#define PERF_CLK_LTC2CLK 4
110#define PERF_CLK_SYS2CLK 5
111#define PERF_CLK_HUB2CLK 6
112#define PERF_CLK_LEGCLK 7
113#define PERF_CLK_MSDCLK 8
114#define PERF_CLK_XCLK 9
115#define PERF_CLK_PWRCLK 10
116#define PERF_CLK_XBAR2CLK 11
117#define PERF_CLK_PCIEGENCLK 12
118#define PERF_CLK_NUM 13
119
120#define BOOT_GPC2CLK_MHZ 2581
121
122u32 clk_pmu_vin_load(struct gk20a *g);
123u32 clk_domain_print_vf_table(struct gk20a *g, u32 clkapidomain);
124u32 clk_domain_get_f_or_v(
125 struct gk20a *g,
126 u32 clkapidomain,
127 u16 *pclkmhz,
128 u32 *pvoltuv,
129 u8 railidx
130);
131int clk_get_fll_clks(struct gk20a *g, struct set_fll_clk *fllclk);
132int clk_set_fll_clks(struct gk20a *g, struct set_fll_clk *fllclk);
133int clk_pmu_freq_controller_load(struct gk20a *g, bool bload, u8 bit_idx);
134u32 nvgpu_clk_vf_change_inject_data_fill_gv10x(struct gk20a *g,
135 struct nv_pmu_clk_rpc *rpccall,
136 struct set_fll_clk *setfllclk);
137u32 nvgpu_clk_vf_change_inject_data_fill_gp10x(struct gk20a *g,
138 struct nv_pmu_clk_rpc *rpccall,
139 struct set_fll_clk *setfllclk);
140u32 nvgpu_clk_set_boot_fll_clk_gv10x(struct gk20a *g);
141int nvgpu_clk_set_fll_clk_gv10x(struct gk20a *g);
142int clk_pmu_freq_effective_avg_load(struct gk20a *g, bool bload);
143u32 clk_freq_effective_avg(struct gk20a *g, u32 clkDomainMask);
144#endif /* NVGPU_CLK_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-30 14:26:00 -0400