Add /proc/gpu#/resubmit_runlist API

Resubmits the runlist in an identical configuration. Causes the
runlist scheduler to:
1. Reload and cache timeslice and scale values from TSGs.
2. Restart scheduling from the head of the runlist [may cause a
   preempt to be scheduled for the currently-running task (?)].
3. Address (?) an errata on Turing where re-enabled channels are
   not always detected.

Above behavior tested on GV100 and partially tested on TU102.

1 files changed, 19 insertions, 0 deletions

diff --git a/runlist.c b/runlist.c
index 22f47ff..91fca82 100644
--- a/runlist.c
+++ b/runlist.c
@@ -137,3 +137,22 @@ int preempt_runlist(struct nvdebug_state *g, uint32_t rl_id) {
         nvdebug_writel(g, NV_PFIFO_RUNLIST_PREEMPT, rl_preempt.raw);
         return 0;
 }
+
+// Read and write runlist configuration, triggering a resubmit
+int resubmit_runlist(struct nvdebug_state *g, uint32_t rl_id) {
+        if (g->chip_id < NV_CHIP_ID_TURING) {
+                eng_runlist_gf100_t rl;
+                if ((rl.raw = nvdebug_readq(g, NV_PFIFO_ENG_RUNLIST_BASE_GF100(rl_id))) == -1)
+                        return -EIO;
+                rl.id = rl_id;
+                nvdebug_writeq(g, NV_PFIFO_RUNLIST_BASE_GF100, rl.raw);
+        } else if (g->chip_id < NV_CHIP_ID_AMPERE) {
+                runlist_submit_tu102_t submit;
+                if ((submit.raw = nvdebug_readq(g, NV_PFIFO_RUNLIST_SUBMIT_TU102(rl_id))) == -1)
+                        return -EIO;
+                nvdebug_writeq(g, NV_PFIFO_RUNLIST_SUBMIT_TU102(rl_id), submit.raw);
+        } else {
+                return -EOPNOTSUPP;
+        }
+        return 0;
+}