diff options
author | Joshua Bakita <bakitajoshua@gmail.com> | 2023-06-28 18:24:25 -0400 |
---|---|---|
committer | Joshua Bakita <bakitajoshua@gmail.com> | 2023-06-28 18:24:25 -0400 |
commit | 01e6fac4d61fdd7fff5433942ec93fc2ea1e4df1 (patch) | |
tree | 4ef34501728a087be24f4ba0af90f91486bf780b /include/volt | |
parent | 306a03d18b305e4e573be3b2931978fa10679eb9 (diff) |
Include nvgpu headers
These are needed to build on NVIDIA's Jetson boards for the time
being. Only a couple structs are required, so it should be fairly
easy to remove this dependency at some point in the future.
Diffstat (limited to 'include/volt')
-rw-r--r-- | include/volt/volt.h | 39 | ||||
-rw-r--r-- | include/volt/volt_dev.c | 609 | ||||
-rw-r--r-- | include/volt/volt_dev.h | 77 | ||||
-rw-r--r-- | include/volt/volt_pmu.c | 384 | ||||
-rw-r--r-- | include/volt/volt_pmu.h | 46 | ||||
-rw-r--r-- | include/volt/volt_policy.c | 513 | ||||
-rw-r--r-- | include/volt/volt_policy.h | 80 | ||||
-rw-r--r-- | include/volt/volt_rail.c | 485 | ||||
-rw-r--r-- | include/volt/volt_rail.h | 90 |
9 files changed, 2323 insertions, 0 deletions
diff --git a/include/volt/volt.h b/include/volt/volt.h new file mode 100644 index 0000000..8b4895f --- /dev/null +++ b/include/volt/volt.h | |||
@@ -0,0 +1,39 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef NVGPU_VOLT_H | ||
24 | #define NVGPU_VOLT_H | ||
25 | |||
26 | #include "volt_rail.h" | ||
27 | #include "volt_dev.h" | ||
28 | #include "volt_policy.h" | ||
29 | #include "volt_pmu.h" | ||
30 | |||
31 | #define VOLTAGE_DESCRIPTOR_TABLE_ENTRY_INVALID 0xFF | ||
32 | |||
33 | struct obj_volt { | ||
34 | struct voltage_rail_metadata volt_rail_metadata; | ||
35 | struct voltage_device_metadata volt_dev_metadata; | ||
36 | struct voltage_policy_metadata volt_policy_metadata; | ||
37 | }; | ||
38 | |||
39 | #endif /* NVGPU_VOLT_H */ | ||
diff --git a/include/volt/volt_dev.c b/include/volt/volt_dev.c new file mode 100644 index 0000000..bb5d182 --- /dev/null +++ b/include/volt/volt_dev.c | |||
@@ -0,0 +1,609 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #include <nvgpu/types.h> | ||
24 | #include <nvgpu/sort.h> | ||
25 | #include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h> | ||
26 | #include <nvgpu/bios.h> | ||
27 | #include <nvgpu/kmem.h> | ||
28 | #include <nvgpu/gk20a.h> | ||
29 | |||
30 | #include "gp106/bios_gp106.h" | ||
31 | |||
32 | #include "boardobj/boardobjgrp.h" | ||
33 | #include "boardobj/boardobjgrp_e32.h" | ||
34 | #include "ctrl/ctrlvolt.h" | ||
35 | |||
36 | #include "volt.h" | ||
37 | |||
38 | #define VOLT_DEV_PWM_VOLTAGE_STEPS_INVALID 0U | ||
39 | #define VOLT_DEV_PWM_VOLTAGE_STEPS_DEFAULT 1U | ||
40 | |||
41 | static int volt_device_pmu_data_init_super(struct gk20a *g, | ||
42 | struct boardobj *pboard_obj, struct nv_pmu_boardobj *ppmudata) | ||
43 | { | ||
44 | int status; | ||
45 | struct voltage_device *pdev; | ||
46 | struct nv_pmu_volt_volt_device_boardobj_set *pset; | ||
47 | |||
48 | status = boardobj_pmudatainit_super(g, pboard_obj, ppmudata); | ||
49 | if (status) { | ||
50 | return status; | ||
51 | } | ||
52 | |||
53 | pdev = (struct voltage_device *)pboard_obj; | ||
54 | pset = (struct nv_pmu_volt_volt_device_boardobj_set *)ppmudata; | ||
55 | |||
56 | pset->switch_delay_us = pdev->switch_delay_us; | ||
57 | pset->voltage_min_uv = pdev->voltage_min_uv; | ||
58 | pset->voltage_max_uv = pdev->voltage_max_uv; | ||
59 | pset->volt_step_uv = pdev->volt_step_uv; | ||
60 | |||
61 | return status; | ||
62 | } | ||
63 | |||
64 | static int volt_device_pmu_data_init_pwm(struct gk20a *g, | ||
65 | struct boardobj *pboard_obj, struct nv_pmu_boardobj *ppmudata) | ||
66 | { | ||
67 | int status = 0; | ||
68 | struct voltage_device_pwm *pdev; | ||
69 | struct nv_pmu_volt_volt_device_pwm_boardobj_set *pset; | ||
70 | |||
71 | status = volt_device_pmu_data_init_super(g, pboard_obj, ppmudata); | ||
72 | if (status) { | ||
73 | return status; | ||
74 | } | ||
75 | |||
76 | pdev = (struct voltage_device_pwm *)pboard_obj; | ||
77 | pset = (struct nv_pmu_volt_volt_device_pwm_boardobj_set *)ppmudata; | ||
78 | |||
79 | pset->raw_period = pdev->raw_period; | ||
80 | pset->voltage_base_uv = pdev->voltage_base_uv; | ||
81 | pset->voltage_offset_scale_uv = pdev->voltage_offset_scale_uv; | ||
82 | pset->pwm_source = pdev->source; | ||
83 | |||
84 | return status; | ||
85 | } | ||
86 | |||
87 | static int construct_volt_device(struct gk20a *g, | ||
88 | struct boardobj **ppboardobj, u16 size, void *pargs) | ||
89 | { | ||
90 | struct voltage_device *ptmp_dev = (struct voltage_device *)pargs; | ||
91 | struct voltage_device *pvolt_dev = NULL; | ||
92 | int status = 0; | ||
93 | |||
94 | status = boardobj_construct_super(g, ppboardobj, size, pargs); | ||
95 | if (status) { | ||
96 | return status; | ||
97 | } | ||
98 | |||
99 | pvolt_dev = (struct voltage_device *)*ppboardobj; | ||
100 | |||
101 | pvolt_dev->volt_domain = ptmp_dev->volt_domain; | ||
102 | pvolt_dev->i2c_dev_idx = ptmp_dev->i2c_dev_idx; | ||
103 | pvolt_dev->switch_delay_us = ptmp_dev->switch_delay_us; | ||
104 | pvolt_dev->rsvd_0 = VOLTAGE_DESCRIPTOR_TABLE_ENTRY_INVALID; | ||
105 | pvolt_dev->rsvd_1 = | ||
106 | VOLTAGE_DESCRIPTOR_TABLE_ENTRY_INVALID; | ||
107 | pvolt_dev->operation_type = ptmp_dev->operation_type; | ||
108 | pvolt_dev->voltage_min_uv = ptmp_dev->voltage_min_uv; | ||
109 | pvolt_dev->voltage_max_uv = ptmp_dev->voltage_max_uv; | ||
110 | |||
111 | pvolt_dev->super.pmudatainit = volt_device_pmu_data_init_super; | ||
112 | |||
113 | return status; | ||
114 | } | ||
115 | |||
116 | static int construct_pwm_volt_device(struct gk20a *g, | ||
117 | struct boardobj **ppboardobj, | ||
118 | u16 size, void *pargs) | ||
119 | { | ||
120 | struct boardobj *pboard_obj = NULL; | ||
121 | struct voltage_device_pwm *ptmp_dev = | ||
122 | (struct voltage_device_pwm *)pargs; | ||
123 | struct voltage_device_pwm *pdev = NULL; | ||
124 | int status = 0; | ||
125 | |||
126 | status = construct_volt_device(g, ppboardobj, size, pargs); | ||
127 | if (status) { | ||
128 | return status; | ||
129 | } | ||
130 | |||
131 | pboard_obj = (*ppboardobj); | ||
132 | pdev = (struct voltage_device_pwm *)*ppboardobj; | ||
133 | |||
134 | pboard_obj->pmudatainit = volt_device_pmu_data_init_pwm; | ||
135 | |||
136 | /* Set VOLTAGE_DEVICE_PWM-specific parameters */ | ||
137 | pdev->voltage_base_uv = ptmp_dev->voltage_base_uv; | ||
138 | pdev->voltage_offset_scale_uv = ptmp_dev->voltage_offset_scale_uv; | ||
139 | pdev->source = ptmp_dev->source; | ||
140 | pdev->raw_period = ptmp_dev->raw_period; | ||
141 | |||
142 | return status; | ||
143 | } | ||
144 | |||
145 | |||
146 | static struct voltage_device_entry *volt_dev_construct_dev_entry_pwm( | ||
147 | struct gk20a *g, | ||
148 | u32 voltage_uv, void *pargs) | ||
149 | { | ||
150 | struct voltage_device_pwm_entry *pentry = NULL; | ||
151 | struct voltage_device_pwm_entry *ptmp_entry = | ||
152 | (struct voltage_device_pwm_entry *)pargs; | ||
153 | |||
154 | pentry = nvgpu_kzalloc(g, sizeof(struct voltage_device_pwm_entry)); | ||
155 | if (pentry == NULL) { | ||
156 | return NULL; | ||
157 | } | ||
158 | |||
159 | memset(pentry, 0, sizeof(struct voltage_device_pwm_entry)); | ||
160 | |||
161 | pentry->super.voltage_uv = voltage_uv; | ||
162 | pentry->duty_cycle = ptmp_entry->duty_cycle; | ||
163 | |||
164 | return (struct voltage_device_entry *)pentry; | ||
165 | } | ||
166 | |||
167 | static u8 volt_dev_operation_type_convert(u8 vbios_type) | ||
168 | { | ||
169 | switch (vbios_type) { | ||
170 | case NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_DEFAULT: | ||
171 | return CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT; | ||
172 | |||
173 | case NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_LPWR_STEADY_STATE: | ||
174 | return CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_STEADY_STATE; | ||
175 | |||
176 | case NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_LPWR_SLEEP_STATE: | ||
177 | return CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_SLEEP_STATE; | ||
178 | } | ||
179 | |||
180 | return CTRL_VOLT_DEVICE_OPERATION_TYPE_INVALID; | ||
181 | } | ||
182 | |||
183 | static struct voltage_device *volt_volt_device_construct(struct gk20a *g, | ||
184 | void *pargs) | ||
185 | { | ||
186 | struct boardobj *pboard_obj = NULL; | ||
187 | |||
188 | if (BOARDOBJ_GET_TYPE(pargs) == CTRL_VOLT_DEVICE_TYPE_PWM) { | ||
189 | int status = construct_pwm_volt_device(g, &pboard_obj, | ||
190 | sizeof(struct voltage_device_pwm), pargs); | ||
191 | if (status) { | ||
192 | nvgpu_err(g, | ||
193 | " Could not allocate memory for VOLTAGE_DEVICE type (%x).", | ||
194 | BOARDOBJ_GET_TYPE(pargs)); | ||
195 | pboard_obj = NULL; | ||
196 | } | ||
197 | } | ||
198 | |||
199 | return (struct voltage_device *)pboard_obj; | ||
200 | } | ||
201 | |||
202 | static int volt_get_voltage_device_table_1x_psv(struct gk20a *g, | ||
203 | struct vbios_voltage_device_table_1x_entry *p_bios_entry, | ||
204 | struct voltage_device_metadata *p_Volt_Device_Meta_Data, | ||
205 | u8 entry_Idx) | ||
206 | { | ||
207 | int status = 0; | ||
208 | u32 entry_cnt = 0; | ||
209 | struct voltage_device *pvolt_dev = NULL; | ||
210 | struct voltage_device_pwm *pvolt_dev_pwm = NULL; | ||
211 | struct voltage_device_pwm *ptmp_dev = NULL; | ||
212 | u32 duty_cycle; | ||
213 | u32 frequency_hz; | ||
214 | u32 voltage_uv; | ||
215 | u8 ext_dev_idx; | ||
216 | u8 steps; | ||
217 | u8 volt_domain = 0; | ||
218 | struct voltage_device_pwm_entry pwm_entry = { { 0 } }; | ||
219 | |||
220 | ptmp_dev = nvgpu_kzalloc(g, sizeof(struct voltage_device_pwm)); | ||
221 | if (ptmp_dev == NULL) { | ||
222 | return -ENOMEM; | ||
223 | } | ||
224 | |||
225 | frequency_hz = (u32)BIOS_GET_FIELD(p_bios_entry->param0, | ||
226 | NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_INPUT_FREQUENCY); | ||
227 | |||
228 | ext_dev_idx = (u8)BIOS_GET_FIELD(p_bios_entry->param0, | ||
229 | NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_EXT_DEVICE_INDEX); | ||
230 | |||
231 | ptmp_dev->super.operation_type = volt_dev_operation_type_convert( | ||
232 | (u8)BIOS_GET_FIELD(p_bios_entry->param1, | ||
233 | NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE)); | ||
234 | |||
235 | if (ptmp_dev->super.operation_type == | ||
236 | CTRL_VOLT_DEVICE_OPERATION_TYPE_INVALID) { | ||
237 | nvgpu_err(g, " Invalid Voltage Device Operation Type."); | ||
238 | |||
239 | status = -EINVAL; | ||
240 | goto done; | ||
241 | } | ||
242 | |||
243 | ptmp_dev->super.voltage_min_uv = | ||
244 | (u32)BIOS_GET_FIELD(p_bios_entry->param1, | ||
245 | NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_VOLTAGE_MINIMUM); | ||
246 | |||
247 | ptmp_dev->super.voltage_max_uv = | ||
248 | (u32)BIOS_GET_FIELD(p_bios_entry->param2, | ||
249 | NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_VOLTAGE_MAXIMUM); | ||
250 | |||
251 | ptmp_dev->voltage_base_uv = BIOS_GET_FIELD(p_bios_entry->param3, | ||
252 | NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_BASE); | ||
253 | |||
254 | steps = (u8)BIOS_GET_FIELD(p_bios_entry->param3, | ||
255 | NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_STEPS); | ||
256 | if (steps == VOLT_DEV_PWM_VOLTAGE_STEPS_INVALID) { | ||
257 | steps = VOLT_DEV_PWM_VOLTAGE_STEPS_DEFAULT; | ||
258 | } | ||
259 | |||
260 | ptmp_dev->voltage_offset_scale_uv = | ||
261 | BIOS_GET_FIELD(p_bios_entry->param4, | ||
262 | NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_OFFSET_SCALE); | ||
263 | |||
264 | volt_domain = volt_rail_vbios_volt_domain_convert_to_internal(g, | ||
265 | (u8)p_bios_entry->volt_domain); | ||
266 | if (volt_domain == CTRL_VOLT_DOMAIN_INVALID) { | ||
267 | nvgpu_err(g, "invalid voltage domain = %d", | ||
268 | (u8)p_bios_entry->volt_domain); | ||
269 | status = -EINVAL; | ||
270 | goto done; | ||
271 | } | ||
272 | |||
273 | if (ptmp_dev->super.operation_type == | ||
274 | CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT) { | ||
275 | if (volt_domain == CTRL_VOLT_DOMAIN_LOGIC) { | ||
276 | ptmp_dev->source = | ||
277 | NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_0; | ||
278 | } | ||
279 | if (volt_domain == CTRL_VOLT_DOMAIN_SRAM) { | ||
280 | ptmp_dev->source = | ||
281 | NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_1; | ||
282 | } | ||
283 | ptmp_dev->raw_period = | ||
284 | g->ops.clk.get_crystal_clk_hz(g) / frequency_hz; | ||
285 | } else if (ptmp_dev->super.operation_type == | ||
286 | CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_STEADY_STATE) { | ||
287 | ptmp_dev->source = NV_PMU_PMGR_PWM_SOURCE_RSVD_0; | ||
288 | ptmp_dev->raw_period = 0; | ||
289 | } else if (ptmp_dev->super.operation_type == | ||
290 | CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_SLEEP_STATE) { | ||
291 | ptmp_dev->source = NV_PMU_PMGR_PWM_SOURCE_RSVD_1; | ||
292 | ptmp_dev->raw_period = 0; | ||
293 | } | ||
294 | |||
295 | /* Initialize data for parent class. */ | ||
296 | ptmp_dev->super.super.type = CTRL_VOLT_DEVICE_TYPE_PWM; | ||
297 | ptmp_dev->super.volt_domain = volt_domain; | ||
298 | ptmp_dev->super.i2c_dev_idx = ext_dev_idx; | ||
299 | ptmp_dev->super.switch_delay_us = (u16)p_bios_entry->settle_time_us; | ||
300 | |||
301 | pvolt_dev = volt_volt_device_construct(g, ptmp_dev); | ||
302 | if (pvolt_dev == NULL) { | ||
303 | nvgpu_err(g, " Failure to construct VOLTAGE_DEVICE object."); | ||
304 | |||
305 | status = -EINVAL; | ||
306 | goto done; | ||
307 | } | ||
308 | |||
309 | status = boardobjgrp_objinsert( | ||
310 | &p_Volt_Device_Meta_Data->volt_devices.super, | ||
311 | (struct boardobj *)pvolt_dev, entry_Idx); | ||
312 | if (status) { | ||
313 | nvgpu_err(g, | ||
314 | "could not add VOLTAGE_DEVICE for entry %d into boardobjgrp ", | ||
315 | entry_Idx); | ||
316 | goto done; | ||
317 | } | ||
318 | |||
319 | pvolt_dev_pwm = (struct voltage_device_pwm *)pvolt_dev; | ||
320 | |||
321 | duty_cycle = 0; | ||
322 | do { | ||
323 | voltage_uv = (u32)(pvolt_dev_pwm->voltage_base_uv + | ||
324 | (s32)((((s64)((s32)duty_cycle)) * | ||
325 | pvolt_dev_pwm->voltage_offset_scale_uv) | ||
326 | / ((s64)((s32) pvolt_dev_pwm->raw_period)))); | ||
327 | |||
328 | /* Skip creating entry for invalid voltage. */ | ||
329 | if ((voltage_uv >= pvolt_dev_pwm->super.voltage_min_uv) && | ||
330 | (voltage_uv <= pvolt_dev_pwm->super.voltage_max_uv)) { | ||
331 | if (pvolt_dev_pwm->voltage_offset_scale_uv < 0) { | ||
332 | pwm_entry.duty_cycle = | ||
333 | pvolt_dev_pwm->raw_period - duty_cycle; | ||
334 | } else { | ||
335 | pwm_entry.duty_cycle = duty_cycle; | ||
336 | } | ||
337 | |||
338 | /* Check if there is room left in the voltage table. */ | ||
339 | if (entry_cnt == VOLTAGE_TABLE_MAX_ENTRIES) { | ||
340 | nvgpu_err(g, "Voltage table is full"); | ||
341 | status = -EINVAL; | ||
342 | goto done; | ||
343 | } | ||
344 | |||
345 | pvolt_dev->pentry[entry_cnt] = | ||
346 | volt_dev_construct_dev_entry_pwm(g, | ||
347 | voltage_uv, &pwm_entry); | ||
348 | if (pvolt_dev->pentry[entry_cnt] == NULL) { | ||
349 | nvgpu_err(g, | ||
350 | " Error creating voltage_device_pwm_entry!"); | ||
351 | status = -EINVAL; | ||
352 | goto done; | ||
353 | } | ||
354 | |||
355 | entry_cnt++; | ||
356 | } | ||
357 | |||
358 | /* Obtain next value after the specified steps. */ | ||
359 | duty_cycle = duty_cycle + (u32)steps; | ||
360 | |||
361 | /* Cap duty cycle to PWM period. */ | ||
362 | if (duty_cycle > pvolt_dev_pwm->raw_period) { | ||
363 | duty_cycle = pvolt_dev_pwm->raw_period; | ||
364 | } | ||
365 | |||
366 | } while (duty_cycle < pvolt_dev_pwm->raw_period); | ||
367 | |||
368 | done: | ||
369 | if (pvolt_dev != NULL) { | ||
370 | pvolt_dev->num_entries = entry_cnt; | ||
371 | } | ||
372 | |||
373 | nvgpu_kfree(g, ptmp_dev); | ||
374 | return status; | ||
375 | } | ||
376 | |||
377 | static u32 volt_get_volt_devices_table(struct gk20a *g, | ||
378 | struct voltage_device_metadata *pvolt_device_metadata) | ||
379 | { | ||
380 | u32 status = 0; | ||
381 | u8 *volt_device_table_ptr = NULL; | ||
382 | struct vbios_voltage_device_table_1x_header header = { 0 }; | ||
383 | struct vbios_voltage_device_table_1x_entry entry = { 0 }; | ||
384 | u8 entry_idx; | ||
385 | u8 *entry_offset; | ||
386 | |||
387 | volt_device_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, | ||
388 | g->bios.perf_token, VOLTAGE_DEVICE_TABLE); | ||
389 | if (volt_device_table_ptr == NULL) { | ||
390 | status = -EINVAL; | ||
391 | goto done; | ||
392 | } | ||
393 | |||
394 | memcpy(&header, volt_device_table_ptr, | ||
395 | sizeof(struct vbios_voltage_device_table_1x_header)); | ||
396 | |||
397 | /* Read in the entries. */ | ||
398 | for (entry_idx = 0; entry_idx < header.num_table_entries; entry_idx++) { | ||
399 | entry_offset = (volt_device_table_ptr + header.header_size + | ||
400 | (entry_idx * header.table_entry_size)); | ||
401 | |||
402 | memcpy(&entry, entry_offset, | ||
403 | sizeof(struct vbios_voltage_device_table_1x_entry)); | ||
404 | |||
405 | if (entry.type == NV_VBIOS_VOLTAGE_DEVICE_1X_ENTRY_TYPE_PSV) { | ||
406 | status = volt_get_voltage_device_table_1x_psv(g, | ||
407 | &entry, pvolt_device_metadata, | ||
408 | entry_idx); | ||
409 | } | ||
410 | } | ||
411 | |||
412 | done: | ||
413 | return status; | ||
414 | } | ||
415 | |||
416 | static int _volt_device_devgrp_pmudata_instget(struct gk20a *g, | ||
417 | struct nv_pmu_boardobjgrp *pmuboardobjgrp, | ||
418 | struct nv_pmu_boardobj **ppboardobjpmudata, u8 idx) | ||
419 | { | ||
420 | struct nv_pmu_volt_volt_device_boardobj_grp_set *pgrp_set = | ||
421 | (struct nv_pmu_volt_volt_device_boardobj_grp_set *) | ||
422 | pmuboardobjgrp; | ||
423 | |||
424 | nvgpu_log_info(g, " "); | ||
425 | |||
426 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | ||
427 | if (((u32)BIT(idx) & | ||
428 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0U) { | ||
429 | return -EINVAL; | ||
430 | } | ||
431 | |||
432 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) | ||
433 | &pgrp_set->objects[idx].data.board_obj; | ||
434 | nvgpu_log_info(g, "Done"); | ||
435 | return 0; | ||
436 | } | ||
437 | |||
438 | static int _volt_device_devgrp_pmustatus_instget(struct gk20a *g, | ||
439 | void *pboardobjgrppmu, | ||
440 | struct nv_pmu_boardobj_query **ppboardobjpmustatus, u8 idx) | ||
441 | { | ||
442 | struct nv_pmu_volt_volt_device_boardobj_grp_get_status *pgrp_get_status | ||
443 | = (struct nv_pmu_volt_volt_device_boardobj_grp_get_status *) | ||
444 | pboardobjgrppmu; | ||
445 | |||
446 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | ||
447 | if (((u32)BIT(idx) & | ||
448 | pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0U) { | ||
449 | return -EINVAL; | ||
450 | } | ||
451 | |||
452 | *ppboardobjpmustatus = (struct nv_pmu_boardobj_query *) | ||
453 | &pgrp_get_status->objects[idx].data.board_obj; | ||
454 | return 0; | ||
455 | } | ||
456 | |||
457 | static int volt_device_volt_cmp(const void *a, const void *b) | ||
458 | { | ||
459 | const struct voltage_device_entry *a_entry = *(const struct voltage_device_entry **)a; | ||
460 | const struct voltage_device_entry *b_entry = *(const struct voltage_device_entry **)b; | ||
461 | |||
462 | return (int)a_entry->voltage_uv - (int)b_entry->voltage_uv; | ||
463 | } | ||
464 | |||
465 | static u32 volt_device_state_init(struct gk20a *g, | ||
466 | struct voltage_device *pvolt_dev) | ||
467 | { | ||
468 | u32 status = 0; | ||
469 | struct voltage_rail *pRail = NULL; | ||
470 | u8 rail_idx = 0; | ||
471 | |||
472 | sort(pvolt_dev->pentry, pvolt_dev->num_entries, | ||
473 | sizeof(*pvolt_dev->pentry), volt_device_volt_cmp, | ||
474 | NULL); | ||
475 | |||
476 | /* Initialize VOLT_DEVICE step size. */ | ||
477 | if (pvolt_dev->num_entries <= VOLTAGE_TABLE_MAX_ENTRIES_ONE) { | ||
478 | pvolt_dev->volt_step_uv = NV_PMU_VOLT_VALUE_0V_IN_UV; | ||
479 | } else { | ||
480 | pvolt_dev->volt_step_uv = (pvolt_dev->pentry[1]->voltage_uv - | ||
481 | pvolt_dev->pentry[0]->voltage_uv); | ||
482 | } | ||
483 | |||
484 | /* Build VOLT_RAIL SW state from VOLT_DEVICE SW state. */ | ||
485 | /* If VOLT_RAIL isn't supported, exit. */ | ||
486 | if (VOLT_RAIL_VOLT_3X_SUPPORTED(&g->perf_pmu.volt)) { | ||
487 | rail_idx = volt_rail_volt_domain_convert_to_idx(g, | ||
488 | pvolt_dev->volt_domain); | ||
489 | if (rail_idx == CTRL_BOARDOBJ_IDX_INVALID) { | ||
490 | nvgpu_err(g, | ||
491 | " could not convert voltage domain to rail index."); | ||
492 | status = -EINVAL; | ||
493 | goto done; | ||
494 | } | ||
495 | |||
496 | pRail = VOLT_GET_VOLT_RAIL(&g->perf_pmu.volt, rail_idx); | ||
497 | if (pRail == NULL) { | ||
498 | nvgpu_err(g, | ||
499 | "could not obtain ptr to rail object from rail index"); | ||
500 | status = -EINVAL; | ||
501 | goto done; | ||
502 | } | ||
503 | |||
504 | status = volt_rail_volt_dev_register(g, pRail, | ||
505 | BOARDOBJ_GET_IDX(pvolt_dev), pvolt_dev->operation_type); | ||
506 | if (status) { | ||
507 | nvgpu_err(g, | ||
508 | "Failed to register the device with rail obj"); | ||
509 | goto done; | ||
510 | } | ||
511 | } | ||
512 | |||
513 | done: | ||
514 | if (status) { | ||
515 | nvgpu_err(g, "Error in building rail sw state device sw"); | ||
516 | } | ||
517 | |||
518 | return status; | ||
519 | } | ||
520 | |||
521 | int volt_dev_pmu_setup(struct gk20a *g) | ||
522 | { | ||
523 | int status; | ||
524 | struct boardobjgrp *pboardobjgrp = NULL; | ||
525 | |||
526 | nvgpu_log_info(g, " "); | ||
527 | |||
528 | pboardobjgrp = &g->perf_pmu.volt.volt_dev_metadata.volt_devices.super; | ||
529 | |||
530 | if (!pboardobjgrp->bconstructed) { | ||
531 | return -EINVAL; | ||
532 | } | ||
533 | |||
534 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); | ||
535 | |||
536 | nvgpu_log_info(g, "Done"); | ||
537 | return status; | ||
538 | } | ||
539 | |||
540 | u32 volt_dev_sw_setup(struct gk20a *g) | ||
541 | { | ||
542 | u32 status = 0; | ||
543 | struct boardobjgrp *pboardobjgrp = NULL; | ||
544 | struct voltage_device *pvolt_device; | ||
545 | u8 i; | ||
546 | |||
547 | nvgpu_log_info(g, " "); | ||
548 | |||
549 | status = boardobjgrpconstruct_e32(g, | ||
550 | &g->perf_pmu.volt.volt_dev_metadata.volt_devices); | ||
551 | if (status) { | ||
552 | nvgpu_err(g, | ||
553 | "error creating boardobjgrp for volt rail, status - 0x%x", | ||
554 | status); | ||
555 | goto done; | ||
556 | } | ||
557 | |||
558 | pboardobjgrp = &g->perf_pmu.volt.volt_dev_metadata.volt_devices.super; | ||
559 | |||
560 | pboardobjgrp->pmudatainstget = _volt_device_devgrp_pmudata_instget; | ||
561 | pboardobjgrp->pmustatusinstget = _volt_device_devgrp_pmustatus_instget; | ||
562 | |||
563 | /* Obtain Voltage Rail Table from VBIOS */ | ||
564 | status = volt_get_volt_devices_table(g, &g->perf_pmu.volt. | ||
565 | volt_dev_metadata); | ||
566 | if (status) { | ||
567 | goto done; | ||
568 | } | ||
569 | |||
570 | /* Populate data for the VOLT_RAIL PMU interface */ | ||
571 | BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, VOLT, VOLT_DEVICE); | ||
572 | |||
573 | status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp, | ||
574 | volt, VOLT, volt_device, VOLT_DEVICE); | ||
575 | if (status) { | ||
576 | nvgpu_err(g, | ||
577 | "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", | ||
578 | status); | ||
579 | goto done; | ||
580 | } | ||
581 | |||
582 | status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g, | ||
583 | &g->perf_pmu.volt.volt_dev_metadata.volt_devices.super, | ||
584 | volt, VOLT, volt_device, VOLT_DEVICE); | ||
585 | if (status) { | ||
586 | nvgpu_err(g, | ||
587 | "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", | ||
588 | status); | ||
589 | goto done; | ||
590 | } | ||
591 | |||
592 | /* update calibration to fuse */ | ||
593 | BOARDOBJGRP_FOR_EACH(&(g->perf_pmu.volt.volt_dev_metadata.volt_devices. | ||
594 | super), | ||
595 | struct voltage_device *, pvolt_device, i) { | ||
596 | status = volt_device_state_init(g, pvolt_device); | ||
597 | if (status) { | ||
598 | nvgpu_err(g, | ||
599 | "failure while executing devices's state init interface"); | ||
600 | nvgpu_err(g, | ||
601 | " railIdx = %d, status = 0x%x", i, status); | ||
602 | goto done; | ||
603 | } | ||
604 | } | ||
605 | |||
606 | done: | ||
607 | nvgpu_log_info(g, " done status %x", status); | ||
608 | return status; | ||
609 | } | ||
diff --git a/include/volt/volt_dev.h b/include/volt/volt_dev.h new file mode 100644 index 0000000..48d93ae --- /dev/null +++ b/include/volt/volt_dev.h | |||
@@ -0,0 +1,77 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef NVGPU_VOLT_DEV_H | ||
24 | #define NVGPU_VOLT_DEV_H | ||
25 | |||
26 | #include "boardobj/boardobj.h" | ||
27 | #include "boardobj/boardobjgrp.h" | ||
28 | #include "ctrl/ctrlvolt.h" | ||
29 | |||
30 | #define VOLTAGE_TABLE_MAX_ENTRIES_ONE 1U | ||
31 | #define VOLTAGE_TABLE_MAX_ENTRIES 256U | ||
32 | |||
33 | struct voltage_device { | ||
34 | struct boardobj super; | ||
35 | u8 volt_domain; | ||
36 | u8 i2c_dev_idx; | ||
37 | u32 switch_delay_us; | ||
38 | u32 num_entries; | ||
39 | struct voltage_device_entry *pentry[VOLTAGE_TABLE_MAX_ENTRIES]; | ||
40 | struct voltage_device_entry *pcurr_entry; | ||
41 | u8 rsvd_0; | ||
42 | u8 rsvd_1; | ||
43 | u8 operation_type; | ||
44 | u32 voltage_min_uv; | ||
45 | u32 voltage_max_uv; | ||
46 | u32 volt_step_uv; | ||
47 | }; | ||
48 | |||
49 | struct voltage_device_entry { | ||
50 | u32 voltage_uv; | ||
51 | }; | ||
52 | |||
53 | struct voltage_device_metadata { | ||
54 | struct boardobjgrp_e32 volt_devices; | ||
55 | }; | ||
56 | |||
57 | /*! | ||
58 | * Extends VOLTAGE_DEVICE providing attributes specific to PWM controllers. | ||
59 | */ | ||
60 | struct voltage_device_pwm { | ||
61 | struct voltage_device super; | ||
62 | s32 voltage_base_uv; | ||
63 | s32 voltage_offset_scale_uv; | ||
64 | enum nv_pmu_pmgr_pwm_source source; | ||
65 | u32 raw_period; | ||
66 | }; | ||
67 | |||
68 | struct voltage_device_pwm_entry { | ||
69 | struct voltage_device_entry super; | ||
70 | u32 duty_cycle; | ||
71 | }; | ||
72 | /* PWM end */ | ||
73 | |||
74 | u32 volt_dev_sw_setup(struct gk20a *g); | ||
75 | int volt_dev_pmu_setup(struct gk20a *g); | ||
76 | |||
77 | #endif /* NVGPU_VOLT_DEV_H */ | ||
diff --git a/include/volt/volt_pmu.c b/include/volt/volt_pmu.c new file mode 100644 index 0000000..2249ae2 --- /dev/null +++ b/include/volt/volt_pmu.c | |||
@@ -0,0 +1,384 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #include <nvgpu/pmu.h> | ||
24 | #include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h> | ||
25 | #include <nvgpu/gk20a.h> | ||
26 | |||
27 | #include "boardobj/boardobjgrp.h" | ||
28 | #include "boardobj/boardobjgrp_e32.h" | ||
29 | #include "gp106/bios_gp106.h" | ||
30 | #include "ctrl/ctrlvolt.h" | ||
31 | #include "ctrl/ctrlperf.h" | ||
32 | |||
33 | #include "volt.h" | ||
34 | |||
35 | #define RAIL_COUNT_GP 2 | ||
36 | #define RAIL_COUNT_GV 1 | ||
37 | |||
38 | struct volt_rpc_pmucmdhandler_params { | ||
39 | struct nv_pmu_volt_rpc *prpc_call; | ||
40 | u32 success; | ||
41 | }; | ||
42 | |||
43 | static void volt_rpc_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg, | ||
44 | void *param, u32 handle, u32 status) | ||
45 | { | ||
46 | struct volt_rpc_pmucmdhandler_params *phandlerparams = | ||
47 | (struct volt_rpc_pmucmdhandler_params *)param; | ||
48 | |||
49 | nvgpu_log_info(g, " "); | ||
50 | |||
51 | if (msg->msg.volt.msg_type != NV_PMU_VOLT_MSG_ID_RPC) { | ||
52 | nvgpu_err(g, "unsupported msg for VOLT RPC %x", | ||
53 | msg->msg.volt.msg_type); | ||
54 | return; | ||
55 | } | ||
56 | |||
57 | if (phandlerparams->prpc_call->b_supported) { | ||
58 | phandlerparams->success = 1; | ||
59 | } | ||
60 | } | ||
61 | |||
62 | |||
63 | static u32 volt_pmu_rpc_execute(struct gk20a *g, | ||
64 | struct nv_pmu_volt_rpc *prpc_call) | ||
65 | { | ||
66 | struct pmu_cmd cmd; | ||
67 | struct pmu_msg msg; | ||
68 | struct pmu_payload payload; | ||
69 | u32 status = 0; | ||
70 | u32 seqdesc; | ||
71 | struct volt_rpc_pmucmdhandler_params handler; | ||
72 | |||
73 | memset(&payload, 0, sizeof(struct pmu_payload)); | ||
74 | memset(&cmd, 0, sizeof(struct pmu_cmd)); | ||
75 | memset(&msg, 0, sizeof(struct pmu_msg)); | ||
76 | memset(&handler, 0, sizeof(struct volt_rpc_pmucmdhandler_params)); | ||
77 | |||
78 | cmd.hdr.unit_id = PMU_UNIT_VOLT; | ||
79 | cmd.hdr.size = (u32)sizeof(struct nv_pmu_volt_cmd) + | ||
80 | (u32)sizeof(struct pmu_hdr); | ||
81 | cmd.cmd.volt.cmd_type = NV_PMU_VOLT_CMD_ID_RPC; | ||
82 | msg.hdr.size = sizeof(struct pmu_msg); | ||
83 | |||
84 | payload.in.buf = (u8 *)prpc_call; | ||
85 | payload.in.size = (u32)sizeof(struct nv_pmu_volt_rpc); | ||
86 | payload.in.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED; | ||
87 | payload.in.offset = NV_PMU_VOLT_CMD_RPC_ALLOC_OFFSET; | ||
88 | |||
89 | payload.out.buf = (u8 *)prpc_call; | ||
90 | payload.out.size = (u32)sizeof(struct nv_pmu_volt_rpc); | ||
91 | payload.out.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED; | ||
92 | payload.out.offset = NV_PMU_VOLT_MSG_RPC_ALLOC_OFFSET; | ||
93 | |||
94 | handler.prpc_call = prpc_call; | ||
95 | handler.success = 0; | ||
96 | |||
97 | status = nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload, | ||
98 | PMU_COMMAND_QUEUE_LPQ, | ||
99 | volt_rpc_pmucmdhandler, (void *)&handler, | ||
100 | &seqdesc, ~0); | ||
101 | if (status) { | ||
102 | nvgpu_err(g, "unable to post volt RPC cmd %x", | ||
103 | cmd.cmd.volt.cmd_type); | ||
104 | goto volt_pmu_rpc_execute; | ||
105 | } | ||
106 | |||
107 | pmu_wait_message_cond(&g->pmu, | ||
108 | gk20a_get_gr_idle_timeout(g), | ||
109 | &handler.success, 1); | ||
110 | |||
111 | if (handler.success == 0U) { | ||
112 | status = -EINVAL; | ||
113 | nvgpu_err(g, "rpc call to volt failed"); | ||
114 | } | ||
115 | |||
116 | volt_pmu_rpc_execute: | ||
117 | return status; | ||
118 | } | ||
119 | |||
120 | u32 nvgpu_volt_send_load_cmd_to_pmu_gp10x(struct gk20a *g) | ||
121 | { | ||
122 | struct nv_pmu_volt_rpc rpc_call = { 0 }; | ||
123 | u32 status = 0; | ||
124 | |||
125 | rpc_call.function = NV_PMU_VOLT_RPC_ID_LOAD; | ||
126 | |||
127 | status = volt_pmu_rpc_execute(g, &rpc_call); | ||
128 | if (status) { | ||
129 | nvgpu_err(g, | ||
130 | "Error while executing LOAD RPC: status = 0x%08x.", | ||
131 | status); | ||
132 | } | ||
133 | |||
134 | return status; | ||
135 | } | ||
136 | |||
137 | u32 nvgpu_volt_send_load_cmd_to_pmu_gv10x(struct gk20a *g) | ||
138 | { | ||
139 | struct nvgpu_pmu *pmu = &g->pmu; | ||
140 | struct nv_pmu_rpc_struct_volt_load rpc; | ||
141 | u32 status = 0; | ||
142 | |||
143 | memset(&rpc, 0, sizeof(struct nv_pmu_rpc_struct_volt_load)); | ||
144 | PMU_RPC_EXECUTE(status, pmu, VOLT, LOAD, &rpc, 0); | ||
145 | if (status) { | ||
146 | nvgpu_err(g, "Failed to execute RPC status=0x%x", | ||
147 | status); | ||
148 | } | ||
149 | |||
150 | return status; | ||
151 | } | ||
152 | |||
153 | u32 nvgpu_volt_rail_get_voltage_gp10x(struct gk20a *g, | ||
154 | u8 volt_domain, u32 *pvoltage_uv) | ||
155 | { | ||
156 | struct nv_pmu_volt_rpc rpc_call = { 0 }; | ||
157 | u32 status = 0; | ||
158 | u8 rail_idx; | ||
159 | |||
160 | rail_idx = volt_rail_volt_domain_convert_to_idx(g, volt_domain); | ||
161 | if ((rail_idx == CTRL_VOLT_RAIL_INDEX_INVALID) || | ||
162 | (!VOLT_RAIL_INDEX_IS_VALID(&g->perf_pmu.volt, rail_idx))) { | ||
163 | nvgpu_err(g, | ||
164 | "failed: volt_domain = %d, voltage rail table = %d.", | ||
165 | volt_domain, rail_idx); | ||
166 | return -EINVAL; | ||
167 | } | ||
168 | |||
169 | /* Set RPC parameters. */ | ||
170 | rpc_call.function = NV_PMU_VOLT_RPC_ID_VOLT_RAIL_GET_VOLTAGE; | ||
171 | rpc_call.params.volt_rail_get_voltage.rail_idx = rail_idx; | ||
172 | |||
173 | /* Execute the voltage get request via PMU RPC. */ | ||
174 | status = volt_pmu_rpc_execute(g, &rpc_call); | ||
175 | if (status) { | ||
176 | nvgpu_err(g, | ||
177 | "Error while executing volt_rail_get_voltage rpc"); | ||
178 | return status; | ||
179 | } | ||
180 | |||
181 | /* Copy out the current voltage. */ | ||
182 | *pvoltage_uv = rpc_call.params.volt_rail_get_voltage.voltage_uv; | ||
183 | |||
184 | return status; | ||
185 | } | ||
186 | |||
187 | u32 nvgpu_volt_rail_get_voltage_gv10x(struct gk20a *g, | ||
188 | u8 volt_domain, u32 *pvoltage_uv) | ||
189 | { | ||
190 | struct nvgpu_pmu *pmu = &g->pmu; | ||
191 | struct nv_pmu_rpc_struct_volt_volt_rail_get_voltage rpc; | ||
192 | u32 status = 0; | ||
193 | u8 rail_idx; | ||
194 | |||
195 | rail_idx = volt_rail_volt_domain_convert_to_idx(g, volt_domain); | ||
196 | if ((rail_idx == CTRL_VOLT_RAIL_INDEX_INVALID) || | ||
197 | (!VOLT_RAIL_INDEX_IS_VALID(&g->perf_pmu.volt, rail_idx))) { | ||
198 | nvgpu_err(g, | ||
199 | "failed: volt_domain = %d, voltage rail table = %d.", | ||
200 | volt_domain, rail_idx); | ||
201 | return -EINVAL; | ||
202 | } | ||
203 | |||
204 | memset(&rpc, 0, | ||
205 | sizeof(struct nv_pmu_rpc_struct_volt_volt_rail_get_voltage)); | ||
206 | rpc.rail_idx = rail_idx; | ||
207 | |||
208 | PMU_RPC_EXECUTE_CPB(status, pmu, VOLT, VOLT_RAIL_GET_VOLTAGE, &rpc, 0); | ||
209 | if (status) { | ||
210 | nvgpu_err(g, "Failed to execute RPC status=0x%x", | ||
211 | status); | ||
212 | } | ||
213 | |||
214 | *pvoltage_uv = rpc.voltage_uv; | ||
215 | |||
216 | return status; | ||
217 | } | ||
218 | |||
219 | static u32 volt_policy_set_voltage(struct gk20a *g, u8 client_id, | ||
220 | struct ctrl_perf_volt_rail_list *prail_list) | ||
221 | { | ||
222 | struct nv_pmu_volt_rpc rpc_call = { 0 }; | ||
223 | struct obj_volt *pvolt = &g->perf_pmu.volt; | ||
224 | u32 status = 0; | ||
225 | u8 policy_idx = CTRL_VOLT_POLICY_INDEX_INVALID; | ||
226 | u8 i = 0; | ||
227 | |||
228 | /* Sanity check input rail list. */ | ||
229 | for (i = 0; i < prail_list->num_rails; i++) { | ||
230 | if ((prail_list->rails[i].volt_domain == | ||
231 | CTRL_VOLT_DOMAIN_INVALID) || | ||
232 | (prail_list->rails[i].voltage_uv == | ||
233 | NV_PMU_VOLT_VALUE_0V_IN_UV)) { | ||
234 | nvgpu_err(g, "Invalid voltage domain or target"); | ||
235 | nvgpu_err(g, " client_id = %d, listEntry = %d", | ||
236 | client_id, i); | ||
237 | nvgpu_err(g, " volt_domain = %d, voltage_uv = %d uV.", | ||
238 | prail_list->rails[i].volt_domain, | ||
239 | prail_list->rails[i].voltage_uv); | ||
240 | status = -EINVAL; | ||
241 | goto exit; | ||
242 | } | ||
243 | } | ||
244 | |||
245 | /* Convert the client ID to index. */ | ||
246 | if (client_id == CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ) { | ||
247 | policy_idx = | ||
248 | pvolt->volt_policy_metadata.perf_core_vf_seq_policy_idx; | ||
249 | } | ||
250 | else { | ||
251 | status = -EINVAL; | ||
252 | goto exit; | ||
253 | } | ||
254 | |||
255 | /* Set RPC parameters. */ | ||
256 | rpc_call.function = NV_PMU_VOLT_RPC_ID_VOLT_POLICY_SET_VOLTAGE; | ||
257 | rpc_call.params.volt_policy_voltage_data.policy_idx = policy_idx; | ||
258 | memcpy(&rpc_call.params.volt_policy_voltage_data.rail_list, prail_list, | ||
259 | (sizeof(struct ctrl_perf_volt_rail_list))); | ||
260 | |||
261 | /* Execute the voltage change request via PMU RPC. */ | ||
262 | status = volt_pmu_rpc_execute(g, &rpc_call); | ||
263 | if (status) { | ||
264 | nvgpu_err(g, | ||
265 | "Error while executing VOLT_POLICY_SET_VOLTAGE RPC"); | ||
266 | } | ||
267 | |||
268 | exit: | ||
269 | return status; | ||
270 | } | ||
271 | |||
272 | static u32 volt_set_voltage_gv10x_rpc(struct gk20a *g, u8 client_id, | ||
273 | struct ctrl_volt_volt_rail_list_v1 *prail_list) | ||
274 | { | ||
275 | struct nvgpu_pmu *pmu = &g->pmu; | ||
276 | struct nv_pmu_rpc_struct_volt_volt_set_voltage rpc; | ||
277 | int status = 0; | ||
278 | |||
279 | memset(&rpc, 0, sizeof(struct nv_pmu_rpc_struct_volt_volt_set_voltage)); | ||
280 | rpc.client_id = 0x1; | ||
281 | rpc.rail_list = *prail_list; | ||
282 | |||
283 | PMU_RPC_EXECUTE_CPB(status, pmu, VOLT, VOLT_SET_VOLTAGE, &rpc, 0); | ||
284 | if (status) { | ||
285 | nvgpu_err(g, "Failed to execute RPC status=0x%x", | ||
286 | status); | ||
287 | } | ||
288 | |||
289 | return status; | ||
290 | } | ||
291 | |||
292 | u32 nvgpu_volt_set_voltage_gv10x(struct gk20a *g, u32 logic_voltage_uv, | ||
293 | u32 sram_voltage_uv) | ||
294 | { | ||
295 | int status = 0; | ||
296 | struct ctrl_volt_volt_rail_list_v1 rail_list = { 0 }; | ||
297 | |||
298 | rail_list.num_rails = RAIL_COUNT_GV; | ||
299 | rail_list.rails[0].rail_idx = | ||
300 | volt_rail_volt_domain_convert_to_idx(g, | ||
301 | CTRL_VOLT_DOMAIN_LOGIC); | ||
302 | rail_list.rails[0].voltage_uv = logic_voltage_uv; | ||
303 | rail_list.rails[0].voltage_min_noise_unaware_uv = logic_voltage_uv; | ||
304 | |||
305 | status = volt_set_voltage_gv10x_rpc(g, | ||
306 | CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ, &rail_list); | ||
307 | |||
308 | return status; | ||
309 | } | ||
310 | |||
311 | u32 nvgpu_volt_set_voltage_gp10x(struct gk20a *g, u32 logic_voltage_uv, | ||
312 | u32 sram_voltage_uv) | ||
313 | { | ||
314 | int status = 0; | ||
315 | struct ctrl_perf_volt_rail_list rail_list = { 0 }; | ||
316 | |||
317 | rail_list.num_rails = RAIL_COUNT_GP; | ||
318 | rail_list.rails[0].volt_domain = CTRL_VOLT_DOMAIN_LOGIC; | ||
319 | rail_list.rails[0].voltage_uv = logic_voltage_uv; | ||
320 | rail_list.rails[0].voltage_min_noise_unaware_uv = logic_voltage_uv; | ||
321 | rail_list.rails[1].volt_domain = CTRL_VOLT_DOMAIN_SRAM; | ||
322 | rail_list.rails[1].voltage_uv = sram_voltage_uv; | ||
323 | rail_list.rails[1].voltage_min_noise_unaware_uv = sram_voltage_uv; | ||
324 | |||
325 | status = volt_policy_set_voltage(g, | ||
326 | CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ, &rail_list); | ||
327 | |||
328 | return status; | ||
329 | } | ||
330 | |||
331 | u32 volt_set_voltage(struct gk20a *g, u32 logic_voltage_uv, u32 sram_voltage_uv) | ||
332 | { | ||
333 | return g->ops.pmu_ver.volt.volt_set_voltage(g, | ||
334 | logic_voltage_uv, sram_voltage_uv); | ||
335 | } | ||
336 | |||
337 | u32 volt_get_voltage(struct gk20a *g, u32 volt_domain, u32 *voltage_uv) | ||
338 | { | ||
339 | return g->ops.pmu_ver.volt.volt_get_voltage(g, | ||
340 | volt_domain, voltage_uv); | ||
341 | } | ||
342 | |||
343 | static int volt_policy_set_noiseaware_vmin(struct gk20a *g, | ||
344 | struct ctrl_volt_volt_rail_list *prail_list) | ||
345 | { | ||
346 | struct nv_pmu_volt_rpc rpc_call = { 0 }; | ||
347 | u32 status = 0; | ||
348 | |||
349 | /* Set RPC parameters. */ | ||
350 | rpc_call.function = NV_PMU_VOLT_RPC_ID_VOLT_RAIL_SET_NOISE_UNAWARE_VMIN; | ||
351 | rpc_call.params.volt_rail_set_noise_unaware_vmin.num_rails = | ||
352 | prail_list->num_rails; | ||
353 | memcpy(&rpc_call.params.volt_rail_set_noise_unaware_vmin.rail_list, | ||
354 | prail_list, (sizeof(struct ctrl_volt_volt_rail_list))); | ||
355 | |||
356 | /* Execute the voltage change request via PMU RPC. */ | ||
357 | status = volt_pmu_rpc_execute(g, &rpc_call); | ||
358 | if (status) { | ||
359 | nvgpu_err(g, | ||
360 | "Error while executing VOLT_POLICY_SET_VOLTAGE RPC"); | ||
361 | return -EINVAL; | ||
362 | } | ||
363 | |||
364 | return 0; | ||
365 | } | ||
366 | |||
367 | int volt_set_noiseaware_vmin(struct gk20a *g, u32 logic_voltage_uv, | ||
368 | u32 sram_voltage_uv) | ||
369 | { | ||
370 | int status = 0; | ||
371 | struct ctrl_volt_volt_rail_list rail_list = { 0 }; | ||
372 | |||
373 | rail_list.num_rails = RAIL_COUNT_GP; | ||
374 | rail_list.rails[0].rail_idx = 0; | ||
375 | rail_list.rails[0].voltage_uv = logic_voltage_uv; | ||
376 | rail_list.rails[1].rail_idx = 1; | ||
377 | rail_list.rails[1].voltage_uv = sram_voltage_uv; | ||
378 | |||
379 | status = volt_policy_set_noiseaware_vmin(g, &rail_list); | ||
380 | |||
381 | return status; | ||
382 | |||
383 | } | ||
384 | |||
diff --git a/include/volt/volt_pmu.h b/include/volt/volt_pmu.h new file mode 100644 index 0000000..c9fb8bf --- /dev/null +++ b/include/volt/volt_pmu.h | |||
@@ -0,0 +1,46 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef NVGPU_VOLT_PMU_H | ||
24 | #define NVGPU_VOLT_PMU_H | ||
25 | |||
26 | u32 volt_pmu_send_load_cmd_to_pmu(struct gk20a *g); | ||
27 | u32 volt_set_voltage(struct gk20a *g, u32 logic_voltage_uv, | ||
28 | u32 sram_voltage_uv); | ||
29 | u32 volt_get_voltage(struct gk20a *g, u32 volt_domain, u32 *voltage_uv); | ||
30 | int volt_set_noiseaware_vmin(struct gk20a *g, u32 logic_voltage_uv, | ||
31 | u32 sram_voltage_uv); | ||
32 | |||
33 | u32 nvgpu_volt_set_voltage_gp10x(struct gk20a *g, u32 logic_voltage_uv, | ||
34 | u32 sram_voltage_uv); | ||
35 | u32 nvgpu_volt_rail_get_voltage_gp10x(struct gk20a *g, | ||
36 | u8 volt_domain, u32 *pvoltage_uv); | ||
37 | u32 nvgpu_volt_send_load_cmd_to_pmu_gp10x(struct gk20a *g); | ||
38 | |||
39 | u32 nvgpu_volt_set_voltage_gv10x(struct gk20a *g, u32 logic_voltage_uv, | ||
40 | u32 sram_voltage_uv); | ||
41 | u32 nvgpu_volt_rail_get_voltage_gv10x(struct gk20a *g, | ||
42 | u8 volt_domain, u32 *pvoltage_uv); | ||
43 | u32 nvgpu_volt_send_load_cmd_to_pmu_gv10x(struct gk20a *g); | ||
44 | |||
45 | |||
46 | #endif /* NVGPU_VOLT_PMU_H */ | ||
diff --git a/include/volt/volt_policy.c b/include/volt/volt_policy.c new file mode 100644 index 0000000..cc60730 --- /dev/null +++ b/include/volt/volt_policy.c | |||
@@ -0,0 +1,513 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #include <nvgpu/bios.h> | ||
24 | #include <nvgpu/gk20a.h> | ||
25 | |||
26 | #include "boardobj/boardobjgrp.h" | ||
27 | #include "boardobj/boardobjgrp_e32.h" | ||
28 | #include "gp106/bios_gp106.h" | ||
29 | #include "ctrl/ctrlvolt.h" | ||
30 | |||
31 | #include "volt.h" | ||
32 | |||
33 | static int volt_policy_pmu_data_init_super(struct gk20a *g, | ||
34 | struct boardobj *pboardobj, struct nv_pmu_boardobj *ppmudata) | ||
35 | { | ||
36 | return boardobj_pmudatainit_super(g, pboardobj, ppmudata); | ||
37 | } | ||
38 | |||
39 | static int construct_volt_policy(struct gk20a *g, | ||
40 | struct boardobj **ppboardobj, u16 size, void *pArgs) | ||
41 | { | ||
42 | struct voltage_policy *pvolt_policy = NULL; | ||
43 | int status = 0; | ||
44 | |||
45 | status = boardobj_construct_super(g, ppboardobj, size, pArgs); | ||
46 | if (status) { | ||
47 | return status; | ||
48 | } | ||
49 | |||
50 | pvolt_policy = (struct voltage_policy *)*ppboardobj; | ||
51 | |||
52 | pvolt_policy->super.pmudatainit = volt_policy_pmu_data_init_super; | ||
53 | |||
54 | return status; | ||
55 | } | ||
56 | |||
57 | static int construct_volt_policy_split_rail(struct gk20a *g, | ||
58 | struct boardobj **ppboardobj, u16 size, void *pArgs) | ||
59 | { | ||
60 | struct voltage_policy_split_rail *ptmp_policy = | ||
61 | (struct voltage_policy_split_rail *)pArgs; | ||
62 | struct voltage_policy_split_rail *pvolt_policy = NULL; | ||
63 | int status = 0; | ||
64 | |||
65 | status = construct_volt_policy(g, ppboardobj, size, pArgs); | ||
66 | if (status) { | ||
67 | return status; | ||
68 | } | ||
69 | |||
70 | pvolt_policy = (struct voltage_policy_split_rail *)*ppboardobj; | ||
71 | |||
72 | pvolt_policy->rail_idx_master = ptmp_policy->rail_idx_master; | ||
73 | pvolt_policy->rail_idx_slave = ptmp_policy->rail_idx_slave; | ||
74 | pvolt_policy->delta_min_vfe_equ_idx = | ||
75 | ptmp_policy->delta_min_vfe_equ_idx; | ||
76 | pvolt_policy->delta_max_vfe_equ_idx = | ||
77 | ptmp_policy->delta_max_vfe_equ_idx; | ||
78 | |||
79 | return status; | ||
80 | } | ||
81 | |||
82 | static int construct_volt_policy_single_rail(struct gk20a *g, | ||
83 | struct boardobj **ppboardobj, u16 size, void *pArgs) | ||
84 | { | ||
85 | struct voltage_policy_single_rail *ptmp_policy = | ||
86 | (struct voltage_policy_single_rail *)pArgs; | ||
87 | struct voltage_policy_single_rail *pvolt_policy = NULL; | ||
88 | int status = 0; | ||
89 | |||
90 | status = construct_volt_policy(g, ppboardobj, size, pArgs); | ||
91 | if (status) { | ||
92 | return status; | ||
93 | } | ||
94 | |||
95 | pvolt_policy = (struct voltage_policy_single_rail *)*ppboardobj; | ||
96 | |||
97 | pvolt_policy->rail_idx = ptmp_policy->rail_idx; | ||
98 | |||
99 | return status; | ||
100 | } | ||
101 | |||
102 | static int volt_policy_pmu_data_init_single_rail(struct gk20a *g, | ||
103 | struct boardobj *pboardobj, struct nv_pmu_boardobj *ppmudata) | ||
104 | { | ||
105 | int status = 0; | ||
106 | struct voltage_policy_single_rail *ppolicy; | ||
107 | struct nv_pmu_volt_volt_policy_sr_boardobj_set *pset; | ||
108 | |||
109 | status = volt_policy_pmu_data_init_super(g, pboardobj, ppmudata); | ||
110 | if (status) { | ||
111 | goto done; | ||
112 | } | ||
113 | |||
114 | ppolicy = (struct voltage_policy_single_rail *)pboardobj; | ||
115 | pset = (struct nv_pmu_volt_volt_policy_sr_boardobj_set *) | ||
116 | ppmudata; | ||
117 | pset->rail_idx = ppolicy->rail_idx; | ||
118 | |||
119 | done: | ||
120 | return status; | ||
121 | } | ||
122 | |||
123 | static int volt_policy_pmu_data_init_sr_multi_step(struct gk20a *g, | ||
124 | struct boardobj *pboardobj, struct nv_pmu_boardobj *ppmudata) | ||
125 | { | ||
126 | int status = 0; | ||
127 | struct voltage_policy_single_rail_multi_step *ppolicy; | ||
128 | struct nv_pmu_volt_volt_policy_sr_multi_step_boardobj_set *pset; | ||
129 | |||
130 | status = volt_policy_pmu_data_init_single_rail(g, pboardobj, ppmudata); | ||
131 | if (status) { | ||
132 | goto done; | ||
133 | } | ||
134 | |||
135 | ppolicy = (struct voltage_policy_single_rail_multi_step *)pboardobj; | ||
136 | pset = (struct nv_pmu_volt_volt_policy_sr_multi_step_boardobj_set *) | ||
137 | ppmudata; | ||
138 | |||
139 | pset->ramp_up_step_size_uv = ppolicy->ramp_up_step_size_uv; | ||
140 | pset->ramp_down_step_size_uv = ppolicy->ramp_down_step_size_uv; | ||
141 | pset->inter_switch_delay_us = ppolicy->inter_switch_delay_us; | ||
142 | |||
143 | done: | ||
144 | return status; | ||
145 | } | ||
146 | |||
147 | static int volt_construct_volt_policy_single_rail_multi_step(struct gk20a *g, | ||
148 | struct boardobj **ppboardobj, u16 size, void *pargs) | ||
149 | { | ||
150 | struct boardobj *pboardobj = NULL; | ||
151 | struct voltage_policy_single_rail_multi_step *p_volt_policy = NULL; | ||
152 | struct voltage_policy_single_rail_multi_step *tmp_policy = | ||
153 | (struct voltage_policy_single_rail_multi_step *)pargs; | ||
154 | int status = 0; | ||
155 | |||
156 | status = construct_volt_policy_single_rail(g, ppboardobj, size, pargs); | ||
157 | if (status) { | ||
158 | return status; | ||
159 | } | ||
160 | |||
161 | pboardobj = (*ppboardobj); | ||
162 | p_volt_policy = (struct voltage_policy_single_rail_multi_step *) | ||
163 | *ppboardobj; | ||
164 | |||
165 | pboardobj->pmudatainit = volt_policy_pmu_data_init_sr_multi_step; | ||
166 | |||
167 | p_volt_policy->ramp_up_step_size_uv = | ||
168 | tmp_policy->ramp_up_step_size_uv; | ||
169 | p_volt_policy->ramp_down_step_size_uv = | ||
170 | tmp_policy->ramp_down_step_size_uv; | ||
171 | p_volt_policy->inter_switch_delay_us = | ||
172 | tmp_policy->inter_switch_delay_us; | ||
173 | |||
174 | return status; | ||
175 | } | ||
176 | |||
177 | static int volt_policy_pmu_data_init_split_rail(struct gk20a *g, | ||
178 | struct boardobj *pboardobj, struct nv_pmu_boardobj *ppmudata) | ||
179 | { | ||
180 | int status = 0; | ||
181 | struct voltage_policy_split_rail *ppolicy; | ||
182 | struct nv_pmu_volt_volt_policy_splt_r_boardobj_set *pset; | ||
183 | |||
184 | status = volt_policy_pmu_data_init_super(g, pboardobj, ppmudata); | ||
185 | if (status) { | ||
186 | goto done; | ||
187 | } | ||
188 | |||
189 | ppolicy = (struct voltage_policy_split_rail *)pboardobj; | ||
190 | pset = (struct nv_pmu_volt_volt_policy_splt_r_boardobj_set *) | ||
191 | ppmudata; | ||
192 | |||
193 | pset->rail_idx_master = ppolicy->rail_idx_master; | ||
194 | pset->rail_idx_slave = ppolicy->rail_idx_slave; | ||
195 | pset->delta_min_vfe_equ_idx = ppolicy->delta_min_vfe_equ_idx; | ||
196 | pset->delta_max_vfe_equ_idx = ppolicy->delta_max_vfe_equ_idx; | ||
197 | pset->offset_delta_min_uv = ppolicy->offset_delta_min_uv; | ||
198 | pset->offset_delta_max_uv = ppolicy->offset_delta_max_uv; | ||
199 | |||
200 | done: | ||
201 | return status; | ||
202 | } | ||
203 | |||
204 | static int volt_construct_volt_policy_split_rail_single_step(struct gk20a *g, | ||
205 | struct boardobj **ppboardobj, u16 size, void *pargs) | ||
206 | { | ||
207 | struct boardobj *pboardobj = NULL; | ||
208 | int status = 0; | ||
209 | |||
210 | status = construct_volt_policy_split_rail(g, ppboardobj, size, pargs); | ||
211 | if (status) { | ||
212 | return status; | ||
213 | } | ||
214 | |||
215 | pboardobj = (*ppboardobj); | ||
216 | pboardobj->pmudatainit = volt_policy_pmu_data_init_split_rail; | ||
217 | |||
218 | return status; | ||
219 | } | ||
220 | |||
221 | static struct voltage_policy *volt_volt_policy_construct(struct gk20a *g, void *pargs) | ||
222 | { | ||
223 | struct boardobj *pboard_obj = NULL; | ||
224 | int status = 0; | ||
225 | |||
226 | switch (BOARDOBJ_GET_TYPE(pargs)) { | ||
227 | case CTRL_VOLT_POLICY_TYPE_SR_SINGLE_STEP: | ||
228 | status = volt_construct_volt_policy_split_rail_single_step(g, | ||
229 | &pboard_obj, | ||
230 | sizeof(struct voltage_policy_split_rail_single_step), | ||
231 | pargs); | ||
232 | if (status) { | ||
233 | nvgpu_err(g, | ||
234 | "Could not allocate memory for voltage_policy"); | ||
235 | pboard_obj = NULL; | ||
236 | } | ||
237 | break; | ||
238 | case CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL_MULTI_STEP: | ||
239 | status = volt_construct_volt_policy_single_rail_multi_step(g, | ||
240 | &pboard_obj, | ||
241 | sizeof(struct voltage_policy_single_rail_multi_step), | ||
242 | pargs); | ||
243 | if (status) { | ||
244 | nvgpu_err(g, | ||
245 | "Could not allocate memory for voltage_policy"); | ||
246 | pboard_obj = NULL; | ||
247 | } | ||
248 | break; | ||
249 | } | ||
250 | |||
251 | return (struct voltage_policy *)pboard_obj; | ||
252 | } | ||
253 | |||
254 | static u8 volt_policy_type_convert(u8 vbios_type) | ||
255 | { | ||
256 | switch (vbios_type) { | ||
257 | case NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL: | ||
258 | return CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL; | ||
259 | |||
260 | case NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_MULTI_STEP: | ||
261 | return CTRL_VOLT_POLICY_TYPE_SR_MULTI_STEP; | ||
262 | |||
263 | case NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_SINGLE_STEP: | ||
264 | return CTRL_VOLT_POLICY_TYPE_SR_SINGLE_STEP; | ||
265 | case NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL_MULTI_STEP: | ||
266 | return CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL_MULTI_STEP; | ||
267 | } | ||
268 | |||
269 | return CTRL_VOLT_POLICY_TYPE_INVALID; | ||
270 | } | ||
271 | |||
272 | static int volt_get_volt_policy_table(struct gk20a *g, | ||
273 | struct voltage_policy_metadata *pvolt_policy_metadata) | ||
274 | { | ||
275 | int status = 0; | ||
276 | u8 *voltage_policy_table_ptr = NULL; | ||
277 | struct voltage_policy *ppolicy = NULL; | ||
278 | struct vbios_voltage_policy_table_1x_header header = { 0 }; | ||
279 | struct vbios_voltage_policy_table_1x_entry entry = { 0 }; | ||
280 | u8 i; | ||
281 | u8 policy_type = 0; | ||
282 | u8 *entry_offset; | ||
283 | union policy_type { | ||
284 | struct boardobj board_obj; | ||
285 | struct voltage_policy volt_policy; | ||
286 | struct voltage_policy_split_rail split_rail; | ||
287 | struct voltage_policy_single_rail_multi_step single_rail_ms; | ||
288 | } policy_type_data; | ||
289 | |||
290 | voltage_policy_table_ptr = | ||
291 | (u8 *)nvgpu_bios_get_perf_table_ptrs(g, | ||
292 | g->bios.perf_token, VOLTAGE_POLICY_TABLE); | ||
293 | if (voltage_policy_table_ptr == NULL) { | ||
294 | status = -EINVAL; | ||
295 | goto done; | ||
296 | } | ||
297 | |||
298 | memcpy(&header, voltage_policy_table_ptr, | ||
299 | sizeof(struct vbios_voltage_policy_table_1x_header)); | ||
300 | |||
301 | /* Set Voltage Policy Table Index for Perf Core VF Sequence client. */ | ||
302 | pvolt_policy_metadata->perf_core_vf_seq_policy_idx = | ||
303 | (u8)header.perf_core_vf_seq_policy_idx; | ||
304 | |||
305 | /* Read in the entries. */ | ||
306 | for (i = 0; i < header.num_table_entries; i++) { | ||
307 | entry_offset = (voltage_policy_table_ptr + header.header_size + | ||
308 | i * header.table_entry_size); | ||
309 | |||
310 | memcpy(&entry, entry_offset, | ||
311 | sizeof(struct vbios_voltage_policy_table_1x_entry)); | ||
312 | |||
313 | memset(&policy_type_data, 0x0, sizeof(policy_type_data)); | ||
314 | |||
315 | policy_type = volt_policy_type_convert((u8)entry.type); | ||
316 | |||
317 | switch (policy_type) { | ||
318 | case CTRL_VOLT_POLICY_TYPE_SR_SINGLE_STEP: | ||
319 | policy_type_data.split_rail.rail_idx_master = | ||
320 | (u8)BIOS_GET_FIELD(entry.param0, | ||
321 | NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_MASTER); | ||
322 | |||
323 | policy_type_data.split_rail.rail_idx_slave = | ||
324 | (u8)BIOS_GET_FIELD(entry.param0, | ||
325 | NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_SLAVE); | ||
326 | |||
327 | policy_type_data.split_rail.delta_min_vfe_equ_idx = | ||
328 | (u8)BIOS_GET_FIELD(entry.param0, | ||
329 | NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MIN); | ||
330 | |||
331 | policy_type_data.split_rail.delta_max_vfe_equ_idx = | ||
332 | (u8)BIOS_GET_FIELD(entry.param0, | ||
333 | NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MAX); | ||
334 | break; | ||
335 | case CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL_MULTI_STEP: | ||
336 | policy_type_data.single_rail_ms.inter_switch_delay_us = | ||
337 | (u16)BIOS_GET_FIELD(entry.param1, | ||
338 | NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE); | ||
339 | policy_type_data.single_rail_ms.ramp_up_step_size_uv = | ||
340 | (u32)BIOS_GET_FIELD(entry.param2, | ||
341 | NV_VBIOS_VPT_ENTRY_PARAM2_SR_RAMP_UP_STEP_SIZE_UV); | ||
342 | policy_type_data.single_rail_ms.ramp_down_step_size_uv = | ||
343 | (u32)BIOS_GET_FIELD(entry.param3, | ||
344 | NV_VBIOS_VPT_ENTRY_PARAM3_SR_RAMP_DOWN_STEP_SIZE_UV); | ||
345 | break; | ||
346 | } | ||
347 | |||
348 | policy_type_data.board_obj.type = policy_type; | ||
349 | |||
350 | ppolicy = volt_volt_policy_construct(g, | ||
351 | (void *)&policy_type_data); | ||
352 | if (ppolicy == NULL) { | ||
353 | nvgpu_err(g, | ||
354 | "Failure to construct VOLT_POLICY object."); | ||
355 | status = -EINVAL; | ||
356 | goto done; | ||
357 | } | ||
358 | |||
359 | status = boardobjgrp_objinsert( | ||
360 | &pvolt_policy_metadata->volt_policies.super, | ||
361 | (struct boardobj *)ppolicy, i); | ||
362 | if (status) { | ||
363 | nvgpu_err(g, | ||
364 | "could not add volt_policy for entry %d into boardobjgrp ", | ||
365 | i); | ||
366 | goto done; | ||
367 | } | ||
368 | } | ||
369 | |||
370 | done: | ||
371 | return status; | ||
372 | } | ||
373 | static int _volt_policy_devgrp_pmudata_instget(struct gk20a *g, | ||
374 | struct nv_pmu_boardobjgrp *pmuboardobjgrp, | ||
375 | struct nv_pmu_boardobj **ppboardobjpmudata, u8 idx) | ||
376 | { | ||
377 | struct nv_pmu_volt_volt_policy_boardobj_grp_set *pgrp_set = | ||
378 | (struct nv_pmu_volt_volt_policy_boardobj_grp_set *) | ||
379 | pmuboardobjgrp; | ||
380 | |||
381 | nvgpu_log_info(g, " "); | ||
382 | |||
383 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | ||
384 | if (((u32)BIT(idx) & | ||
385 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0U) { | ||
386 | return -EINVAL; | ||
387 | } | ||
388 | |||
389 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) | ||
390 | &pgrp_set->objects[idx].data.board_obj; | ||
391 | nvgpu_log_info(g, " Done"); | ||
392 | return 0; | ||
393 | } | ||
394 | |||
395 | static int _volt_policy_devgrp_pmustatus_instget(struct gk20a *g, | ||
396 | void *pboardobjgrppmu, | ||
397 | struct nv_pmu_boardobj_query **ppboardobjpmustatus, u8 idx) | ||
398 | { | ||
399 | struct nv_pmu_volt_volt_policy_boardobj_grp_get_status *p_get_status = | ||
400 | (struct nv_pmu_volt_volt_policy_boardobj_grp_get_status *) | ||
401 | pboardobjgrppmu; | ||
402 | |||
403 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | ||
404 | if (((u32)BIT(idx) & | ||
405 | p_get_status->hdr.data.super.obj_mask.super.data[0]) == 0U) { | ||
406 | return -EINVAL; | ||
407 | } | ||
408 | |||
409 | *ppboardobjpmustatus = (struct nv_pmu_boardobj_query *) | ||
410 | &p_get_status->objects[idx].data.board_obj; | ||
411 | return 0; | ||
412 | } | ||
413 | |||
414 | static int _volt_policy_grp_pmudatainit_super(struct gk20a *g, | ||
415 | struct boardobjgrp *pboardobjgrp, | ||
416 | struct nv_pmu_boardobjgrp_super *pboardobjgrppmu) | ||
417 | { | ||
418 | struct nv_pmu_volt_volt_policy_boardobjgrp_set_header *pset = | ||
419 | (struct nv_pmu_volt_volt_policy_boardobjgrp_set_header *) | ||
420 | pboardobjgrppmu; | ||
421 | struct obj_volt *volt = (struct obj_volt *)pboardobjgrp; | ||
422 | int status = 0; | ||
423 | |||
424 | status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu); | ||
425 | if (status) { | ||
426 | nvgpu_err(g, | ||
427 | "error updating pmu boardobjgrp for volt policy 0x%x", | ||
428 | status); | ||
429 | goto done; | ||
430 | } | ||
431 | pset->perf_core_vf_seq_policy_idx = | ||
432 | volt->volt_policy_metadata.perf_core_vf_seq_policy_idx; | ||
433 | |||
434 | done: | ||
435 | return status; | ||
436 | } | ||
437 | |||
438 | int volt_policy_pmu_setup(struct gk20a *g) | ||
439 | { | ||
440 | int status; | ||
441 | struct boardobjgrp *pboardobjgrp = NULL; | ||
442 | |||
443 | nvgpu_log_info(g, " "); | ||
444 | |||
445 | pboardobjgrp = | ||
446 | &g->perf_pmu.volt.volt_policy_metadata.volt_policies.super; | ||
447 | |||
448 | if (!pboardobjgrp->bconstructed) { | ||
449 | return -EINVAL; | ||
450 | } | ||
451 | |||
452 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); | ||
453 | |||
454 | nvgpu_log_info(g, "Done"); | ||
455 | return status; | ||
456 | } | ||
457 | |||
458 | int volt_policy_sw_setup(struct gk20a *g) | ||
459 | { | ||
460 | int status = 0; | ||
461 | struct boardobjgrp *pboardobjgrp = NULL; | ||
462 | |||
463 | nvgpu_log_info(g, " "); | ||
464 | |||
465 | status = boardobjgrpconstruct_e32(g, | ||
466 | &g->perf_pmu.volt.volt_policy_metadata.volt_policies); | ||
467 | if (status) { | ||
468 | nvgpu_err(g, | ||
469 | "error creating boardobjgrp for volt rail, status - 0x%x", | ||
470 | status); | ||
471 | goto done; | ||
472 | } | ||
473 | |||
474 | pboardobjgrp = | ||
475 | &g->perf_pmu.volt.volt_policy_metadata.volt_policies.super; | ||
476 | |||
477 | pboardobjgrp->pmudatainstget = _volt_policy_devgrp_pmudata_instget; | ||
478 | pboardobjgrp->pmustatusinstget = _volt_policy_devgrp_pmustatus_instget; | ||
479 | pboardobjgrp->pmudatainit = _volt_policy_grp_pmudatainit_super; | ||
480 | |||
481 | /* Obtain Voltage Rail Table from VBIOS */ | ||
482 | status = volt_get_volt_policy_table(g, &g->perf_pmu.volt. | ||
483 | volt_policy_metadata); | ||
484 | if (status) { | ||
485 | goto done; | ||
486 | } | ||
487 | |||
488 | /* Populate data for the VOLT_RAIL PMU interface */ | ||
489 | BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, VOLT, VOLT_POLICY); | ||
490 | |||
491 | status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp, | ||
492 | volt, VOLT, volt_policy, VOLT_POLICY); | ||
493 | if (status) { | ||
494 | nvgpu_err(g, | ||
495 | "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", | ||
496 | status); | ||
497 | goto done; | ||
498 | } | ||
499 | |||
500 | status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g, | ||
501 | &g->perf_pmu.volt.volt_policy_metadata.volt_policies.super, | ||
502 | volt, VOLT, volt_policy, VOLT_POLICY); | ||
503 | if (status) { | ||
504 | nvgpu_err(g, | ||
505 | "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", | ||
506 | status); | ||
507 | goto done; | ||
508 | } | ||
509 | |||
510 | done: | ||
511 | nvgpu_log_info(g, " done status %x", status); | ||
512 | return status; | ||
513 | } | ||
diff --git a/include/volt/volt_policy.h b/include/volt/volt_policy.h new file mode 100644 index 0000000..06f5aa3 --- /dev/null +++ b/include/volt/volt_policy.h | |||
@@ -0,0 +1,80 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef NVGPU_VOLT_POLICY_H | ||
24 | #define NVGPU_VOLT_POLICY_H | ||
25 | |||
26 | #define VOLT_POLICY_INDEX_IS_VALID(pvolt, policy_idx) \ | ||
27 | (boardobjgrp_idxisvalid( \ | ||
28 | &((pvolt)->volt_policy_metadata.volt_policies.super), \ | ||
29 | (policy_idx))) | ||
30 | |||
31 | /*! | ||
32 | * extends boardobj providing attributes common to all voltage_policies. | ||
33 | */ | ||
34 | struct voltage_policy { | ||
35 | struct boardobj super; | ||
36 | }; | ||
37 | |||
38 | struct voltage_policy_metadata { | ||
39 | u8 perf_core_vf_seq_policy_idx; | ||
40 | struct boardobjgrp_e32 volt_policies; | ||
41 | }; | ||
42 | |||
43 | /*! | ||
44 | * extends voltage_policy providing attributes | ||
45 | * common to all voltage_policy_split_rail. | ||
46 | */ | ||
47 | struct voltage_policy_split_rail { | ||
48 | struct voltage_policy super; | ||
49 | u8 rail_idx_master; | ||
50 | u8 rail_idx_slave; | ||
51 | u8 delta_min_vfe_equ_idx; | ||
52 | u8 delta_max_vfe_equ_idx; | ||
53 | s32 offset_delta_min_uv; | ||
54 | s32 offset_delta_max_uv; | ||
55 | }; | ||
56 | |||
57 | struct voltage_policy_split_rail_single_step { | ||
58 | struct voltage_policy_split_rail super; | ||
59 | }; | ||
60 | |||
61 | struct voltage_policy_split_rail_multi_step { | ||
62 | struct voltage_policy_split_rail super; | ||
63 | u16 inter_switch_delay_us; | ||
64 | }; | ||
65 | |||
66 | struct voltage_policy_single_rail { | ||
67 | struct voltage_policy super; | ||
68 | u8 rail_idx; | ||
69 | }; | ||
70 | |||
71 | struct voltage_policy_single_rail_multi_step { | ||
72 | struct voltage_policy_single_rail super; | ||
73 | u16 inter_switch_delay_us; | ||
74 | u32 ramp_up_step_size_uv; | ||
75 | u32 ramp_down_step_size_uv; | ||
76 | }; | ||
77 | |||
78 | int volt_policy_sw_setup(struct gk20a *g); | ||
79 | int volt_policy_pmu_setup(struct gk20a *g); | ||
80 | #endif /* NVGPU_VOLT_POLICY_H */ | ||
diff --git a/include/volt/volt_rail.c b/include/volt/volt_rail.c new file mode 100644 index 0000000..caf297f --- /dev/null +++ b/include/volt/volt_rail.c | |||
@@ -0,0 +1,485 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #include <nvgpu/bios.h> | ||
24 | #include <nvgpu/gk20a.h> | ||
25 | |||
26 | #include "boardobj/boardobjgrp.h" | ||
27 | #include "boardobj/boardobjgrp_e32.h" | ||
28 | #include "gp106/bios_gp106.h" | ||
29 | #include "ctrl/ctrlvolt.h" | ||
30 | |||
31 | #include "volt.h" | ||
32 | |||
33 | u8 volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain) | ||
34 | { | ||
35 | switch (g->perf_pmu.volt.volt_rail_metadata.volt_domain_hal) { | ||
36 | case CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL: | ||
37 | switch (volt_domain) { | ||
38 | case CTRL_VOLT_DOMAIN_LOGIC: | ||
39 | return 0; | ||
40 | } | ||
41 | break; | ||
42 | case CTRL_VOLT_DOMAIN_HAL_GP10X_SPLIT_RAIL: | ||
43 | switch (volt_domain) { | ||
44 | case CTRL_VOLT_DOMAIN_LOGIC: | ||
45 | return 0; | ||
46 | case CTRL_VOLT_DOMAIN_SRAM: | ||
47 | return 1; | ||
48 | } | ||
49 | break; | ||
50 | } | ||
51 | |||
52 | return CTRL_BOARDOBJ_IDX_INVALID; | ||
53 | } | ||
54 | |||
55 | u32 volt_rail_volt_dev_register(struct gk20a *g, struct voltage_rail | ||
56 | *pvolt_rail, u8 volt_dev_idx, u8 operation_type) | ||
57 | { | ||
58 | u32 status = 0; | ||
59 | |||
60 | if (operation_type == CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT) { | ||
61 | if (pvolt_rail->volt_dev_idx_default == | ||
62 | CTRL_BOARDOBJ_IDX_INVALID) { | ||
63 | pvolt_rail->volt_dev_idx_default = volt_dev_idx; | ||
64 | } else { | ||
65 | status = -EINVAL; | ||
66 | goto exit; | ||
67 | } | ||
68 | } else if (operation_type == | ||
69 | CTRL_VOLT_VOLT_DEVICE_OPERATION_TYPE_IPC_VMIN) { | ||
70 | if (pvolt_rail->volt_dev_idx_ipc_vmin == | ||
71 | CTRL_BOARDOBJ_IDX_INVALID) { | ||
72 | pvolt_rail->volt_dev_idx_ipc_vmin = volt_dev_idx; | ||
73 | /* | ||
74 | * Exit on purpose as we do not want to register | ||
75 | * IPC_VMIN device against the rail to avoid | ||
76 | * setting current voltage instead of | ||
77 | * IPC Vmin voltage. | ||
78 | */ | ||
79 | goto exit; | ||
80 | } else { | ||
81 | status = -EINVAL; | ||
82 | goto exit; | ||
83 | } | ||
84 | } else { | ||
85 | goto exit; | ||
86 | } | ||
87 | |||
88 | status = boardobjgrpmask_bitset(&pvolt_rail->volt_dev_mask.super, | ||
89 | volt_dev_idx); | ||
90 | |||
91 | exit: | ||
92 | if (status) { | ||
93 | nvgpu_err(g, "Failed to register VOLTAGE_DEVICE"); | ||
94 | } | ||
95 | |||
96 | return status; | ||
97 | } | ||
98 | |||
99 | static u32 volt_rail_state_init(struct gk20a *g, | ||
100 | struct voltage_rail *pvolt_rail) | ||
101 | { | ||
102 | u32 status = 0; | ||
103 | u32 i; | ||
104 | |||
105 | pvolt_rail->volt_dev_idx_default = CTRL_BOARDOBJ_IDX_INVALID; | ||
106 | |||
107 | for (i = 0; i < CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES; i++) { | ||
108 | pvolt_rail->volt_delta_uv[i] = (int)NV_PMU_VOLT_VALUE_0V_IN_UV; | ||
109 | g->perf_pmu.volt.volt_rail_metadata.ext_rel_delta_uv[i] = | ||
110 | NV_PMU_VOLT_VALUE_0V_IN_UV; | ||
111 | } | ||
112 | |||
113 | pvolt_rail->volt_margin_limit_vfe_equ_mon_handle = | ||
114 | NV_PMU_PERF_RPC_VFE_EQU_MONITOR_COUNT_MAX; | ||
115 | pvolt_rail->rel_limit_vfe_equ_mon_handle = | ||
116 | NV_PMU_PERF_RPC_VFE_EQU_MONITOR_COUNT_MAX; | ||
117 | pvolt_rail->alt_rel_limit_vfe_equ_mon_handle = | ||
118 | NV_PMU_PERF_RPC_VFE_EQU_MONITOR_COUNT_MAX; | ||
119 | pvolt_rail->ov_limit_vfe_equ_mon_handle = | ||
120 | NV_PMU_PERF_RPC_VFE_EQU_MONITOR_COUNT_MAX; | ||
121 | |||
122 | status = boardobjgrpmask_e32_init(&pvolt_rail->volt_dev_mask, NULL); | ||
123 | if (status) { | ||
124 | nvgpu_err(g, | ||
125 | "Failed to initialize BOARDOBJGRPMASK of VOLTAGE_DEVICEs"); | ||
126 | } | ||
127 | |||
128 | return status; | ||
129 | } | ||
130 | |||
131 | static int volt_rail_init_pmudata_super(struct gk20a *g, | ||
132 | struct boardobj *board_obj_ptr, struct nv_pmu_boardobj *ppmudata) | ||
133 | { | ||
134 | int status = 0; | ||
135 | struct voltage_rail *prail; | ||
136 | struct nv_pmu_volt_volt_rail_boardobj_set *rail_pmu_data; | ||
137 | u32 i; | ||
138 | |||
139 | nvgpu_log_info(g, " "); | ||
140 | |||
141 | status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); | ||
142 | if (status) { | ||
143 | return status; | ||
144 | } | ||
145 | |||
146 | prail = (struct voltage_rail *)board_obj_ptr; | ||
147 | rail_pmu_data = (struct nv_pmu_volt_volt_rail_boardobj_set *) | ||
148 | ppmudata; | ||
149 | |||
150 | rail_pmu_data->rel_limit_vfe_equ_idx = prail->rel_limit_vfe_equ_idx; | ||
151 | rail_pmu_data->alt_rel_limit_vfe_equ_idx = | ||
152 | prail->alt_rel_limit_vfe_equ_idx; | ||
153 | rail_pmu_data->ov_limit_vfe_equ_idx = prail->ov_limit_vfe_equ_idx; | ||
154 | rail_pmu_data->vmin_limit_vfe_equ_idx = prail->vmin_limit_vfe_equ_idx; | ||
155 | rail_pmu_data->volt_margin_limit_vfe_equ_idx = | ||
156 | prail->volt_margin_limit_vfe_equ_idx; | ||
157 | rail_pmu_data->pwr_equ_idx = prail->pwr_equ_idx; | ||
158 | rail_pmu_data->volt_dev_idx_default = prail->volt_dev_idx_default; | ||
159 | rail_pmu_data->volt_scale_exp_pwr_equ_idx = | ||
160 | prail->volt_scale_exp_pwr_equ_idx; | ||
161 | rail_pmu_data->volt_dev_idx_ipc_vmin = prail->volt_dev_idx_ipc_vmin; | ||
162 | |||
163 | for (i = 0; i < CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES; i++) { | ||
164 | rail_pmu_data->volt_delta_uv[i] = prail->volt_delta_uv[i] + | ||
165 | (int)g->perf_pmu.volt.volt_rail_metadata.ext_rel_delta_uv[i]; | ||
166 | } | ||
167 | |||
168 | status = boardobjgrpmask_export(&prail->volt_dev_mask.super, | ||
169 | prail->volt_dev_mask.super.bitcount, | ||
170 | &rail_pmu_data->volt_dev_mask.super); | ||
171 | if (status) { | ||
172 | nvgpu_err(g, | ||
173 | "Failed to export BOARDOBJGRPMASK of VOLTAGE_DEVICEs"); | ||
174 | } | ||
175 | |||
176 | nvgpu_log_info(g, "Done"); | ||
177 | |||
178 | return status; | ||
179 | } | ||
180 | |||
181 | static struct voltage_rail *construct_volt_rail(struct gk20a *g, void *pargs) | ||
182 | { | ||
183 | struct boardobj *board_obj_ptr = NULL; | ||
184 | struct voltage_rail *ptemp_rail = (struct voltage_rail *)pargs; | ||
185 | struct voltage_rail *board_obj_volt_rail_ptr = NULL; | ||
186 | int status; | ||
187 | |||
188 | nvgpu_log_info(g, " "); | ||
189 | status = boardobj_construct_super(g, &board_obj_ptr, | ||
190 | sizeof(struct voltage_rail), pargs); | ||
191 | if (status) { | ||
192 | return NULL; | ||
193 | } | ||
194 | |||
195 | board_obj_volt_rail_ptr = (struct voltage_rail *)board_obj_ptr; | ||
196 | /* override super class interface */ | ||
197 | board_obj_ptr->pmudatainit = volt_rail_init_pmudata_super; | ||
198 | |||
199 | board_obj_volt_rail_ptr->boot_voltage_uv = | ||
200 | ptemp_rail->boot_voltage_uv; | ||
201 | board_obj_volt_rail_ptr->rel_limit_vfe_equ_idx = | ||
202 | ptemp_rail->rel_limit_vfe_equ_idx; | ||
203 | board_obj_volt_rail_ptr->alt_rel_limit_vfe_equ_idx = | ||
204 | ptemp_rail->alt_rel_limit_vfe_equ_idx; | ||
205 | board_obj_volt_rail_ptr->ov_limit_vfe_equ_idx = | ||
206 | ptemp_rail->ov_limit_vfe_equ_idx; | ||
207 | board_obj_volt_rail_ptr->pwr_equ_idx = | ||
208 | ptemp_rail->pwr_equ_idx; | ||
209 | board_obj_volt_rail_ptr->boot_volt_vfe_equ_idx = | ||
210 | ptemp_rail->boot_volt_vfe_equ_idx; | ||
211 | board_obj_volt_rail_ptr->vmin_limit_vfe_equ_idx = | ||
212 | ptemp_rail->vmin_limit_vfe_equ_idx; | ||
213 | board_obj_volt_rail_ptr->volt_margin_limit_vfe_equ_idx = | ||
214 | ptemp_rail->volt_margin_limit_vfe_equ_idx; | ||
215 | board_obj_volt_rail_ptr->volt_scale_exp_pwr_equ_idx = | ||
216 | ptemp_rail->volt_scale_exp_pwr_equ_idx; | ||
217 | |||
218 | nvgpu_log_info(g, "Done"); | ||
219 | |||
220 | return (struct voltage_rail *)board_obj_ptr; | ||
221 | } | ||
222 | |||
223 | u8 volt_rail_vbios_volt_domain_convert_to_internal(struct gk20a *g, | ||
224 | u8 vbios_volt_domain) | ||
225 | { | ||
226 | switch (g->perf_pmu.volt.volt_rail_metadata.volt_domain_hal) { | ||
227 | case CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL: | ||
228 | if (vbios_volt_domain == 0U) { | ||
229 | return CTRL_VOLT_DOMAIN_LOGIC; | ||
230 | } | ||
231 | break; | ||
232 | case CTRL_VOLT_DOMAIN_HAL_GP10X_SPLIT_RAIL: | ||
233 | switch (vbios_volt_domain) { | ||
234 | case 0: | ||
235 | return CTRL_VOLT_DOMAIN_LOGIC; | ||
236 | case 1: | ||
237 | return CTRL_VOLT_DOMAIN_SRAM; | ||
238 | } | ||
239 | break; | ||
240 | } | ||
241 | |||
242 | return CTRL_VOLT_DOMAIN_INVALID; | ||
243 | } | ||
244 | |||
245 | int volt_rail_pmu_setup(struct gk20a *g) | ||
246 | { | ||
247 | int status; | ||
248 | struct boardobjgrp *pboardobjgrp = NULL; | ||
249 | |||
250 | nvgpu_log_info(g, " "); | ||
251 | |||
252 | pboardobjgrp = &g->perf_pmu.volt.volt_rail_metadata.volt_rails.super; | ||
253 | |||
254 | if (!pboardobjgrp->bconstructed) { | ||
255 | return -EINVAL; | ||
256 | } | ||
257 | |||
258 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); | ||
259 | |||
260 | nvgpu_log_info(g, "Done"); | ||
261 | return status; | ||
262 | } | ||
263 | |||
264 | static int volt_get_volt_rail_table(struct gk20a *g, | ||
265 | struct voltage_rail_metadata *pvolt_rail_metadata) | ||
266 | { | ||
267 | int status = 0; | ||
268 | u8 *volt_rail_table_ptr = NULL; | ||
269 | struct voltage_rail *prail = NULL; | ||
270 | struct vbios_voltage_rail_table_1x_header header = { 0 }; | ||
271 | struct vbios_voltage_rail_table_1x_entry entry = { 0 }; | ||
272 | u8 i; | ||
273 | u8 volt_domain; | ||
274 | u8 *entry_ptr; | ||
275 | union rail_type { | ||
276 | struct boardobj board_obj; | ||
277 | struct voltage_rail volt_rail; | ||
278 | } rail_type_data; | ||
279 | |||
280 | volt_rail_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, | ||
281 | g->bios.perf_token, VOLTAGE_RAIL_TABLE); | ||
282 | if (volt_rail_table_ptr == NULL) { | ||
283 | status = -EINVAL; | ||
284 | goto done; | ||
285 | } | ||
286 | |||
287 | memcpy(&header, volt_rail_table_ptr, | ||
288 | sizeof(struct vbios_voltage_rail_table_1x_header)); | ||
289 | |||
290 | pvolt_rail_metadata->volt_domain_hal = (u8)header.volt_domain_hal; | ||
291 | |||
292 | for (i = 0; i < header.num_table_entries; i++) { | ||
293 | entry_ptr = (volt_rail_table_ptr + header.header_size + | ||
294 | (i * header.table_entry_size)); | ||
295 | |||
296 | memset(&rail_type_data, 0x0, sizeof(rail_type_data)); | ||
297 | |||
298 | memcpy(&entry, entry_ptr, | ||
299 | sizeof(struct vbios_voltage_rail_table_1x_entry)); | ||
300 | |||
301 | volt_domain = volt_rail_vbios_volt_domain_convert_to_internal(g, | ||
302 | i); | ||
303 | if (volt_domain == CTRL_VOLT_DOMAIN_INVALID) { | ||
304 | continue; | ||
305 | } | ||
306 | |||
307 | rail_type_data.board_obj.type = volt_domain; | ||
308 | rail_type_data.volt_rail.boot_voltage_uv = | ||
309 | (u32)entry.boot_voltage_uv; | ||
310 | rail_type_data.volt_rail.rel_limit_vfe_equ_idx = | ||
311 | (u8)entry.rel_limit_vfe_equ_idx; | ||
312 | rail_type_data.volt_rail.alt_rel_limit_vfe_equ_idx = | ||
313 | (u8)entry.alt_rel_limit_vfe_equidx; | ||
314 | rail_type_data.volt_rail.ov_limit_vfe_equ_idx = | ||
315 | (u8)entry.ov_limit_vfe_equ_idx; | ||
316 | |||
317 | if (header.table_entry_size >= | ||
318 | NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0C) { | ||
319 | rail_type_data.volt_rail.volt_scale_exp_pwr_equ_idx = | ||
320 | (u8)entry.volt_scale_exp_pwr_equ_idx; | ||
321 | } else { | ||
322 | rail_type_data.volt_rail.volt_scale_exp_pwr_equ_idx = | ||
323 | CTRL_BOARDOBJ_IDX_INVALID; | ||
324 | } | ||
325 | |||
326 | if (header.table_entry_size >= | ||
327 | NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0B) { | ||
328 | rail_type_data.volt_rail.volt_margin_limit_vfe_equ_idx = | ||
329 | (u8)entry.volt_margin_limit_vfe_equ_idx; | ||
330 | } else { | ||
331 | rail_type_data.volt_rail.volt_margin_limit_vfe_equ_idx = | ||
332 | CTRL_BOARDOBJ_IDX_INVALID; | ||
333 | } | ||
334 | |||
335 | if (header.table_entry_size >= | ||
336 | NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0A) { | ||
337 | rail_type_data.volt_rail.vmin_limit_vfe_equ_idx = | ||
338 | (u8)entry.vmin_limit_vfe_equ_idx; | ||
339 | } else { | ||
340 | rail_type_data.volt_rail.vmin_limit_vfe_equ_idx = | ||
341 | CTRL_BOARDOBJ_IDX_INVALID; | ||
342 | } | ||
343 | |||
344 | if (header.table_entry_size >= | ||
345 | NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_09) { | ||
346 | rail_type_data.volt_rail.boot_volt_vfe_equ_idx = | ||
347 | (u8)entry.boot_volt_vfe_equ_idx; | ||
348 | } else { | ||
349 | rail_type_data.volt_rail.boot_volt_vfe_equ_idx = | ||
350 | CTRL_BOARDOBJ_IDX_INVALID; | ||
351 | } | ||
352 | |||
353 | if (header.table_entry_size >= | ||
354 | NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_08) { | ||
355 | rail_type_data.volt_rail.pwr_equ_idx = | ||
356 | (u8)entry.pwr_equ_idx; | ||
357 | } else { | ||
358 | rail_type_data.volt_rail.pwr_equ_idx = | ||
359 | CTRL_PMGR_PWR_EQUATION_INDEX_INVALID; | ||
360 | } | ||
361 | |||
362 | prail = construct_volt_rail(g, &rail_type_data); | ||
363 | |||
364 | status = boardobjgrp_objinsert( | ||
365 | &pvolt_rail_metadata->volt_rails.super, | ||
366 | (struct boardobj *)prail, i); | ||
367 | } | ||
368 | |||
369 | done: | ||
370 | return status; | ||
371 | } | ||
372 | |||
373 | static int _volt_rail_devgrp_pmudata_instget(struct gk20a *g, | ||
374 | struct nv_pmu_boardobjgrp *pmuboardobjgrp, struct nv_pmu_boardobj | ||
375 | **ppboardobjpmudata, u8 idx) | ||
376 | { | ||
377 | struct nv_pmu_volt_volt_rail_boardobj_grp_set *pgrp_set = | ||
378 | (struct nv_pmu_volt_volt_rail_boardobj_grp_set *) | ||
379 | pmuboardobjgrp; | ||
380 | |||
381 | nvgpu_log_info(g, " "); | ||
382 | |||
383 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | ||
384 | if (((u32)BIT(idx) & | ||
385 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0U) { | ||
386 | return -EINVAL; | ||
387 | } | ||
388 | |||
389 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) | ||
390 | &pgrp_set->objects[idx].data.board_obj; | ||
391 | nvgpu_log_info(g, " Done"); | ||
392 | return 0; | ||
393 | } | ||
394 | |||
395 | static int _volt_rail_devgrp_pmustatus_instget(struct gk20a *g, | ||
396 | void *pboardobjgrppmu, struct nv_pmu_boardobj_query | ||
397 | **ppboardobjpmustatus, u8 idx) | ||
398 | { | ||
399 | struct nv_pmu_volt_volt_rail_boardobj_grp_get_status *pgrp_get_status = | ||
400 | (struct nv_pmu_volt_volt_rail_boardobj_grp_get_status *) | ||
401 | pboardobjgrppmu; | ||
402 | |||
403 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | ||
404 | if (((u32)BIT(idx) & | ||
405 | pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0U) { | ||
406 | return -EINVAL; | ||
407 | } | ||
408 | |||
409 | *ppboardobjpmustatus = (struct nv_pmu_boardobj_query *) | ||
410 | &pgrp_get_status->objects[idx].data.board_obj; | ||
411 | return 0; | ||
412 | } | ||
413 | |||
414 | int volt_rail_sw_setup(struct gk20a *g) | ||
415 | { | ||
416 | int status = 0; | ||
417 | struct boardobjgrp *pboardobjgrp = NULL; | ||
418 | struct voltage_rail *pvolt_rail; | ||
419 | u8 i; | ||
420 | |||
421 | nvgpu_log_info(g, " "); | ||
422 | |||
423 | status = boardobjgrpconstruct_e32(g, | ||
424 | &g->perf_pmu.volt.volt_rail_metadata.volt_rails); | ||
425 | if (status) { | ||
426 | nvgpu_err(g, | ||
427 | "error creating boardobjgrp for volt rail, status - 0x%x", | ||
428 | status); | ||
429 | goto done; | ||
430 | } | ||
431 | |||
432 | pboardobjgrp = &g->perf_pmu.volt.volt_rail_metadata.volt_rails.super; | ||
433 | |||
434 | pboardobjgrp->pmudatainstget = _volt_rail_devgrp_pmudata_instget; | ||
435 | pboardobjgrp->pmustatusinstget = _volt_rail_devgrp_pmustatus_instget; | ||
436 | |||
437 | g->perf_pmu.volt.volt_rail_metadata.pct_delta = | ||
438 | NV_PMU_VOLT_VALUE_0V_IN_UV; | ||
439 | |||
440 | /* Obtain Voltage Rail Table from VBIOS */ | ||
441 | status = volt_get_volt_rail_table(g, &g->perf_pmu.volt. | ||
442 | volt_rail_metadata); | ||
443 | if (status) { | ||
444 | goto done; | ||
445 | } | ||
446 | |||
447 | /* Populate data for the VOLT_RAIL PMU interface */ | ||
448 | BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, VOLT, VOLT_RAIL); | ||
449 | |||
450 | status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp, | ||
451 | volt, VOLT, volt_rail, VOLT_RAIL); | ||
452 | if (status) { | ||
453 | nvgpu_err(g, | ||
454 | "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", | ||
455 | status); | ||
456 | goto done; | ||
457 | } | ||
458 | |||
459 | status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g, | ||
460 | &g->perf_pmu.volt.volt_rail_metadata.volt_rails.super, | ||
461 | volt, VOLT, volt_rail, VOLT_RAIL); | ||
462 | if (status) { | ||
463 | nvgpu_err(g, | ||
464 | "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", | ||
465 | status); | ||
466 | goto done; | ||
467 | } | ||
468 | |||
469 | /* update calibration to fuse */ | ||
470 | BOARDOBJGRP_FOR_EACH(&(g->perf_pmu.volt.volt_rail_metadata. | ||
471 | volt_rails.super), | ||
472 | struct voltage_rail *, pvolt_rail, i) { | ||
473 | status = volt_rail_state_init(g, pvolt_rail); | ||
474 | if (status) { | ||
475 | nvgpu_err(g, | ||
476 | "Failure while executing RAIL's state init railIdx = %d", | ||
477 | i); | ||
478 | goto done; | ||
479 | } | ||
480 | } | ||
481 | |||
482 | done: | ||
483 | nvgpu_log_info(g, " done status %x", status); | ||
484 | return status; | ||
485 | } | ||
diff --git a/include/volt/volt_rail.h b/include/volt/volt_rail.h new file mode 100644 index 0000000..72bb254 --- /dev/null +++ b/include/volt/volt_rail.h | |||
@@ -0,0 +1,90 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | |||
24 | #ifndef NVGPU_VOLT_RAIL_H | ||
25 | #define NVGPU_VOLT_RAIL_H | ||
26 | |||
27 | #include "boardobj/boardobj.h" | ||
28 | #include "boardobj/boardobjgrp.h" | ||
29 | |||
30 | #define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES 0x04U | ||
31 | #define CTRL_PMGR_PWR_EQUATION_INDEX_INVALID 0xFFU | ||
32 | |||
33 | #define VOLT_GET_VOLT_RAIL(pvolt, rail_idx) \ | ||
34 | ((struct voltage_rail *)BOARDOBJGRP_OBJ_GET_BY_IDX( \ | ||
35 | &((pvolt)->volt_rail_metadata.volt_rails.super), (rail_idx))) | ||
36 | |||
37 | #define VOLT_RAIL_INDEX_IS_VALID(pvolt, rail_idx) \ | ||
38 | (boardobjgrp_idxisvalid( \ | ||
39 | &((pvolt)->volt_rail_metadata.volt_rails.super), (rail_idx))) | ||
40 | |||
41 | #define VOLT_RAIL_VOLT_3X_SUPPORTED(pvolt) \ | ||
42 | (!BOARDOBJGRP_IS_EMPTY(&((pvolt)->volt_rail_metadata.volt_rails.super))) | ||
43 | |||
44 | /*! | ||
45 | * extends boardobj providing attributes common to all voltage_rails. | ||
46 | */ | ||
47 | struct voltage_rail { | ||
48 | struct boardobj super; | ||
49 | u32 boot_voltage_uv; | ||
50 | u8 rel_limit_vfe_equ_idx; | ||
51 | u8 alt_rel_limit_vfe_equ_idx; | ||
52 | u8 ov_limit_vfe_equ_idx; | ||
53 | u8 pwr_equ_idx; | ||
54 | u8 volt_scale_exp_pwr_equ_idx; | ||
55 | u8 volt_dev_idx_default; | ||
56 | u8 volt_dev_idx_ipc_vmin; | ||
57 | u8 boot_volt_vfe_equ_idx; | ||
58 | u8 vmin_limit_vfe_equ_idx; | ||
59 | u8 volt_margin_limit_vfe_equ_idx; | ||
60 | u32 volt_margin_limit_vfe_equ_mon_handle; | ||
61 | u32 rel_limit_vfe_equ_mon_handle; | ||
62 | u32 alt_rel_limit_vfe_equ_mon_handle; | ||
63 | u32 ov_limit_vfe_equ_mon_handle; | ||
64 | struct boardobjgrpmask_e32 volt_dev_mask; | ||
65 | s32 volt_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES]; | ||
66 | }; | ||
67 | |||
68 | /*! | ||
69 | * metadata of voltage rail functionality. | ||
70 | */ | ||
71 | struct voltage_rail_metadata { | ||
72 | u8 volt_domain_hal; | ||
73 | u8 pct_delta; | ||
74 | u32 ext_rel_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES]; | ||
75 | u8 logic_rail_idx; | ||
76 | u8 sram_rail_idx; | ||
77 | struct boardobjgrp_e32 volt_rails; | ||
78 | }; | ||
79 | |||
80 | u8 volt_rail_vbios_volt_domain_convert_to_internal | ||
81 | (struct gk20a *g, u8 vbios_volt_domain); | ||
82 | |||
83 | u32 volt_rail_volt_dev_register(struct gk20a *g, struct voltage_rail | ||
84 | *pvolt_rail, u8 volt_dev_idx, u8 operation_type); | ||
85 | |||
86 | u8 volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain); | ||
87 | |||
88 | int volt_rail_sw_setup(struct gk20a *g); | ||
89 | int volt_rail_pmu_setup(struct gk20a *g); | ||
90 | #endif /* NVGPU_VOLT_RAIL_H */ | ||