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authorJoshua Bakita <bakitajoshua@gmail.com>2024-09-25 16:09:09 -0400
committerJoshua Bakita <bakitajoshua@gmail.com>2024-09-25 16:09:09 -0400
commitf347fde22f1297e4f022600d201780d5ead78114 (patch)
tree76be305d6187003a1e0486ff6e91efb1062ae118 /include/os/linux/sysfs.c
parent8340d234d78a7d0f46c11a584de538148b78b7cb (diff)
Delete no-longer-needed nvgpu headers
The dependency on these was removed in commit 8340d234.
Diffstat (limited to 'include/os/linux/sysfs.c')
-rw-r--r--include/os/linux/sysfs.c1275
1 files changed, 0 insertions, 1275 deletions
diff --git a/include/os/linux/sysfs.c b/include/os/linux/sysfs.c
deleted file mode 100644
index 221ea0c..0000000
--- a/include/os/linux/sysfs.c
+++ /dev/null
@@ -1,1275 +0,0 @@
1/*
2 * Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/device.h>
18#include <linux/pm_runtime.h>
19#include <linux/fb.h>
20
21#include <nvgpu/kmem.h>
22#include <nvgpu/nvhost.h>
23#include <nvgpu/ptimer.h>
24#include <nvgpu/power_features/cg.h>
25#include <nvgpu/power_features/pg.h>
26
27#include "os_linux.h"
28#include "sysfs.h"
29#include "platform_gk20a.h"
30#include "gk20a/gr_gk20a.h"
31#include "gv11b/gr_gv11b.h"
32
33#define PTIMER_FP_FACTOR 1000000
34
35#define ROOTRW (S_IRWXU|S_IRGRP|S_IROTH)
36
37#define TPC_MASK_FOR_ALL_ACTIVE_TPCs (u32) 0x0
38
39static ssize_t elcg_enable_store(struct device *dev,
40 struct device_attribute *attr, const char *buf, size_t count)
41{
42 struct gk20a *g = get_gk20a(dev);
43 unsigned long val = 0;
44 int err;
45
46 if (kstrtoul(buf, 10, &val) < 0)
47 return -EINVAL;
48
49 err = gk20a_busy(g);
50 if (err)
51 return err;
52
53 if (val) {
54 nvgpu_cg_elcg_set_elcg_enabled(g, true);
55 } else {
56 nvgpu_cg_elcg_set_elcg_enabled(g, false);
57 }
58
59 gk20a_idle(g);
60
61 nvgpu_info(g, "ELCG is %s.", val ? "enabled" :
62 "disabled");
63
64 return count;
65}
66
67static ssize_t elcg_enable_read(struct device *dev,
68 struct device_attribute *attr, char *buf)
69{
70 struct gk20a *g = get_gk20a(dev);
71
72 return snprintf(buf, PAGE_SIZE, "%d\n", g->elcg_enabled ? 1 : 0);
73}
74
75static DEVICE_ATTR(elcg_enable, ROOTRW, elcg_enable_read, elcg_enable_store);
76
77static ssize_t blcg_enable_store(struct device *dev,
78 struct device_attribute *attr, const char *buf, size_t count)
79{
80 struct gk20a *g = get_gk20a(dev);
81 unsigned long val = 0;
82 int err;
83
84 if (kstrtoul(buf, 10, &val) < 0)
85 return -EINVAL;
86
87 err = gk20a_busy(g);
88 if (err)
89 return err;
90
91 if (val) {
92 nvgpu_cg_blcg_set_blcg_enabled(g, true);
93 } else {
94 nvgpu_cg_blcg_set_blcg_enabled(g, false);
95 }
96
97 gk20a_idle(g);
98
99 nvgpu_info(g, "BLCG is %s.", val ? "enabled" :
100 "disabled");
101
102 return count;
103}
104
105static ssize_t blcg_enable_read(struct device *dev,
106 struct device_attribute *attr, char *buf)
107{
108 struct gk20a *g = get_gk20a(dev);
109
110 return snprintf(buf, PAGE_SIZE, "%d\n", g->blcg_enabled ? 1 : 0);
111}
112
113
114static DEVICE_ATTR(blcg_enable, ROOTRW, blcg_enable_read, blcg_enable_store);
115
116static ssize_t slcg_enable_store(struct device *dev,
117 struct device_attribute *attr, const char *buf, size_t count)
118{
119 struct gk20a *g = get_gk20a(dev);
120 unsigned long val = 0;
121 int err;
122
123 if (kstrtoul(buf, 10, &val) < 0)
124 return -EINVAL;
125
126 err = gk20a_busy(g);
127 if (err) {
128 return err;
129 }
130
131 if (val) {
132 nvgpu_cg_slcg_set_slcg_enabled(g, true);
133 } else {
134 nvgpu_cg_slcg_set_slcg_enabled(g, false);
135 }
136
137 /*
138 * TODO: slcg_therm_load_gating is not enabled anywhere during
139 * init. Therefore, it would be incongruous to add it here. Once
140 * it is added to init, we should add it here too.
141 */
142 gk20a_idle(g);
143
144 nvgpu_info(g, "SLCG is %s.", val ? "enabled" :
145 "disabled");
146
147 return count;
148}
149
150static ssize_t slcg_enable_read(struct device *dev,
151 struct device_attribute *attr, char *buf)
152{
153 struct gk20a *g = get_gk20a(dev);
154
155 return snprintf(buf, PAGE_SIZE, "%d\n", g->slcg_enabled ? 1 : 0);
156}
157
158static DEVICE_ATTR(slcg_enable, ROOTRW, slcg_enable_read, slcg_enable_store);
159
160static ssize_t ptimer_scale_factor_show(struct device *dev,
161 struct device_attribute *attr,
162 char *buf)
163{
164 struct gk20a *g = get_gk20a(dev);
165 struct gk20a_platform *platform = dev_get_drvdata(dev);
166 u32 src_freq_hz = platform->ptimer_src_freq;
167 u32 scaling_factor_fp;
168 ssize_t res;
169
170 if (!src_freq_hz) {
171 nvgpu_err(g, "reference clk_m rate is not set correctly");
172 return -EINVAL;
173 }
174
175 scaling_factor_fp = (u32)(PTIMER_REF_FREQ_HZ) /
176 ((u32)(src_freq_hz) /
177 (u32)(PTIMER_FP_FACTOR));
178 res = snprintf(buf,
179 PAGE_SIZE,
180 "%u.%u\n",
181 scaling_factor_fp / PTIMER_FP_FACTOR,
182 scaling_factor_fp % PTIMER_FP_FACTOR);
183
184 return res;
185
186}
187
188static DEVICE_ATTR(ptimer_scale_factor,
189 S_IRUGO,
190 ptimer_scale_factor_show,
191 NULL);
192
193static ssize_t ptimer_ref_freq_show(struct device *dev,
194 struct device_attribute *attr,
195 char *buf)
196{
197 struct gk20a *g = get_gk20a(dev);
198 struct gk20a_platform *platform = dev_get_drvdata(dev);
199 u32 src_freq_hz = platform->ptimer_src_freq;
200 ssize_t res;
201
202 if (!src_freq_hz) {
203 nvgpu_err(g, "reference clk_m rate is not set correctly");
204 return -EINVAL;
205 }
206
207 res = snprintf(buf, PAGE_SIZE, "%u\n", PTIMER_REF_FREQ_HZ);
208
209 return res;
210
211}
212
213static DEVICE_ATTR(ptimer_ref_freq,
214 S_IRUGO,
215 ptimer_ref_freq_show,
216 NULL);
217
218static ssize_t ptimer_src_freq_show(struct device *dev,
219 struct device_attribute *attr,
220 char *buf)
221{
222 struct gk20a *g = get_gk20a(dev);
223 struct gk20a_platform *platform = dev_get_drvdata(dev);