diff options
| author | Joshua Bakita <bakitajoshua@gmail.com> | 2024-09-25 16:09:09 -0400 |
|---|---|---|
| committer | Joshua Bakita <bakitajoshua@gmail.com> | 2024-09-25 16:09:09 -0400 |
| commit | f347fde22f1297e4f022600d201780d5ead78114 (patch) | |
| tree | 76be305d6187003a1e0486ff6e91efb1062ae118 /include/os/linux/nvlink.c | |
| parent | 8340d234d78a7d0f46c11a584de538148b78b7cb (diff) | |
Delete no-longer-needed nvgpu headers
The dependency on these was removed in commit 8340d234.
Diffstat (limited to 'include/os/linux/nvlink.c')
| -rw-r--r-- | include/os/linux/nvlink.c | 132 |
1 files changed, 0 insertions, 132 deletions
diff --git a/include/os/linux/nvlink.c b/include/os/linux/nvlink.c deleted file mode 100644 index dd7c02c..0000000 --- a/include/os/linux/nvlink.c +++ /dev/null | |||
| @@ -1,132 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify it | ||
| 5 | * under the terms and conditions of the GNU General Public License, | ||
| 6 | * version 2, as published by the Free Software Foundation. | ||
| 7 | * | ||
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 11 | * more details. | ||
| 12 | * | ||
| 13 | * You should have received a copy of the GNU General Public License | ||
| 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifdef CONFIG_TEGRA_NVLINK | ||
| 18 | #include <linux/platform/tegra/tegra-nvlink.h> | ||
| 19 | #endif | ||
| 20 | |||
| 21 | #include <nvgpu/gk20a.h> | ||
| 22 | #include <nvgpu/nvlink.h> | ||
| 23 | #include <nvgpu/enabled.h> | ||
| 24 | #include "module.h" | ||
| 25 | |||
| 26 | #ifdef CONFIG_TEGRA_NVLINK | ||
| 27 | int nvgpu_nvlink_read_dt_props(struct gk20a *g) | ||
| 28 | { | ||
| 29 | struct device_node *np; | ||
| 30 | struct nvlink_device *ndev = g->nvlink.priv; | ||
| 31 | u32 local_dev_id; | ||
| 32 | u32 local_link_id; | ||
| 33 | u32 remote_dev_id; | ||
| 34 | u32 remote_link_id; | ||
| 35 | bool is_master; | ||
| 36 | |||
| 37 | /* Parse DT */ | ||
| 38 | np = nvgpu_get_node(g); | ||
| 39 | if (!np) | ||
| 40 | goto fail; | ||
| 41 | |||
| 42 | np = of_get_child_by_name(np, "nvidia,nvlink"); | ||
| 43 | if (!np) | ||
| 44 | goto fail; | ||
| 45 | |||
| 46 | np = of_get_child_by_name(np, "endpoint"); | ||
| 47 | if (!np) | ||
| 48 | goto fail; | ||
| 49 | |||
| 50 | /* Parse DT structure to detect endpoint topology */ | ||
| 51 | of_property_read_u32(np, "local_dev_id", &local_dev_id); | ||
| 52 | of_property_read_u32(np, "local_link_id", &local_link_id); | ||
| 53 | of_property_read_u32(np, "remote_dev_id", &remote_dev_id); | ||
| 54 | of_property_read_u32(np, "remote_link_id", &remote_link_id); | ||
| 55 | is_master = of_property_read_bool(np, "is_master"); | ||
| 56 | |||
| 57 | /* Check that we are in dGPU mode */ | ||
| 58 | if (local_dev_id != NVLINK_ENDPT_GV100) { | ||
| 59 | nvgpu_err(g, "Local nvlink device is not dGPU"); | ||
| 60 | return -EINVAL; | ||
| 61 | } | ||
| 62 | |||
| 63 | ndev->is_master = is_master; | ||
| 64 | ndev->device_id = local_dev_id; | ||
| 65 | ndev->link.link_id = local_link_id; | ||
| 66 | ndev->link.remote_dev_info.device_id = remote_dev_id; | ||
| 67 | ndev->link.remote_dev_info.link_id = remote_link_id; | ||
| 68 | |||
| 69 | return 0; | ||
| 70 | |||
| 71 | fail: | ||
| 72 | nvgpu_info(g, "nvlink endpoint not found or invaling in DT"); | ||
| 73 | return -ENODEV; | ||
| 74 | } | ||
| 75 | #endif /* CONFIG_TEGRA_NVLINK */ | ||
| 76 | |||
| 77 | void nvgpu_mss_nvlink_init_credits(struct gk20a *g) | ||
| 78 | { | ||
| 79 | /* MSS_NVLINK_1_BASE */ | ||
| 80 | void __iomem *soc1 = ioremap(0x01f20010, 4096); | ||
| 81 | /* MSS_NVLINK_2_BASE */ | ||
| 82 | void __iomem *soc2 = ioremap(0x01f40010, 4096); | ||
| 83 | /* MSS_NVLINK_3_BASE */ | ||
| 84 | void __iomem *soc3 = ioremap(0x01f60010, 4096); | ||
| 85 | /* MSS_NVLINK_4_BASE */ | ||
| 86 | void __iomem *soc4 = ioremap(0x01f80010, 4096); | ||
| 87 | u32 val; | ||
| 88 | |||
| 89 | nvgpu_log(g, gpu_dbg_info, "init nvlink soc credits"); | ||
| 90 | |||
| 91 | val = readl_relaxed(soc1); | ||
| 92 | writel_relaxed(val, soc1); | ||
| 93 | val = readl_relaxed(soc1 + 4); | ||
| 94 | writel_relaxed(val, soc1 + 4); | ||
| 95 | |||
| 96 | val = readl_relaxed(soc2); | ||
| 97 | writel_relaxed(val, soc2); | ||
| 98 | val = readl_relaxed(soc2 + 4); | ||
| 99 | writel_relaxed(val, soc2 + 4); | ||
| 100 | |||
| 101 | val = readl_relaxed(soc3); | ||
| 102 | writel_relaxed(val, soc3); | ||
| 103 | val = readl_relaxed(soc3 + 4); | ||
| 104 | writel_relaxed(val, soc3 + 4); | ||
| 105 | |||
| 106 | val = readl_relaxed(soc4); | ||
| 107 | writel_relaxed(val, soc4); | ||
| 108 | val = readl_relaxed(soc4 + 4); | ||
| 109 | writel_relaxed(val, soc4 + 4); | ||
| 110 | } | ||
| 111 | |||
| 112 | int nvgpu_nvlink_deinit(struct gk20a *g) | ||
| 113 | { | ||
| 114 | #ifdef CONFIG_TEGRA_NVLINK | ||
| 115 | struct nvlink_device *ndev = g->nvlink.priv; | ||
| 116 | int err; | ||
| 117 | |||
| 118 | if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_NVLINK)) | ||
| 119 | return -ENODEV; | ||
| 120 | |||
| 121 | err = nvlink_shutdown(ndev); | ||
| 122 | if (err) { | ||
| 123 | nvgpu_err(g, "failed to shut down nvlink"); | ||
| 124 | return err; | ||
| 125 | } | ||
| 126 | |||
| 127 | nvgpu_nvlink_remove(g); | ||
| 128 | |||
| 129 | return 0; | ||
| 130 | #endif | ||
| 131 | return -ENODEV; | ||
| 132 | } | ||
