Include nvgpu headers

These are needed to build on NVIDIA's Jetson boards for the time
being. Only a couple structs are required, so it should be fairly
easy to remove this dependency at some point in the future.

1 files changed, 750 insertions, 0 deletions

diff --git a/include/os/linux/ioctl_tsg.c b/include/os/linux/ioctl_tsg.c
new file mode 100644
index 0000000..2f8cb3a
--- /dev/null
+++ b/include/os/linux/ioctl_tsg.c
@@ -0,0 +1,750 @@
+/*
+ * Copyright (c) 2014-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/fs.h>
+#include <linux/file.h>
+#include <linux/cdev.h>
+#include <linux/uaccess.h>
+#include <linux/poll.h>
+#include <uapi/linux/nvgpu.h>
+#include <linux/anon_inodes.h>
+
+#include <nvgpu/kmem.h>
+#include <nvgpu/log.h>
+#include <nvgpu/os_sched.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/channel.h>
+#include <nvgpu/tsg.h>
+
+#include "gv11b/fifo_gv11b.h"
+#include "platform_gk20a.h"
+#include "ioctl_tsg.h"
+#include "ioctl_channel.h"
+#include "os_linux.h"
+
+struct tsg_private {
+        struct gk20a *g;
+        struct tsg_gk20a *tsg;
+};
+
+static int gk20a_tsg_bind_channel_fd(struct tsg_gk20a *tsg, int ch_fd)
+{
+        struct channel_gk20a *ch;
+        int err;
+
+        ch = gk20a_get_channel_from_file(ch_fd);
+        if (!ch)
+                return -EINVAL;
+
+        err = ch->g->ops.fifo.tsg_bind_channel(tsg, ch);
+
+        gk20a_channel_put(ch);
+        return err;
+}
+
+static int gk20a_tsg_ioctl_bind_channel_ex(struct gk20a *g,
+        struct tsg_gk20a *tsg, struct nvgpu_tsg_bind_channel_ex_args *arg)
+{
+        struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
+        struct channel_gk20a *ch;
+        struct gr_gk20a *gr = &g->gr;
+        int err = 0;
+
+        nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "tsgid=%u", tsg->tsgid);
+
+        nvgpu_mutex_acquire(&sched->control_lock);
+        if (sched->control_locked) {
+                err = -EPERM;
+                goto mutex_release;
+        }
+        err = gk20a_busy(g);
+        if (err) {
+                nvgpu_err(g, "failed to power on gpu");
+                goto mutex_release;
+        }
+
+        ch = gk20a_get_channel_from_file(arg->channel_fd);
+        if (!ch) {
+                err = -EINVAL;
+                goto idle;
+        }
+
+        if (arg->tpc_pg_enabled && (!tsg->tpc_num_initialized)) {
+                if ((arg->num_active_tpcs > gr->max_tpc_count) ||
+                                !(arg->num_active_tpcs)) {
+                        nvgpu_err(g, "Invalid num of active TPCs");
+                        err = -EINVAL;
+                        goto ch_put;
+                }
+                tsg->tpc_num_initialized = true;
+                tsg->num_active_tpcs = arg->num_active_tpcs;
+                tsg->tpc_pg_enabled = true;
+        } else {
+                tsg->tpc_pg_enabled = false; nvgpu_log(g, gpu_dbg_info, "dynamic TPC-PG not enabled");
+        }
+
+        if (arg->subcontext_id < g->fifo.max_subctx_count) {
+                ch->subctx_id = arg->subcontext_id;
+        } else {
+                err = -EINVAL;
+                goto ch_put;
+        }
+
+        nvgpu_log(g, gpu_dbg_info, "channel id : %d : subctx: %d",
+                                ch->chid, ch->subctx_id);
+
+        /* Use runqueue selector 1 for all ASYNC ids */
+        if (ch->subctx_id > CHANNEL_INFO_VEID0)
+                ch->runqueue_sel = 1;
+
+        err = ch->g->ops.fifo.tsg_bind_channel(tsg, ch);
+ch_put:
+        gk20a_channel_put(ch);
+idle:
+        gk20a_idle(g);
+mutex_release:
+        nvgpu_mutex_release(&sched->control_lock);
+        return err;
+}
+
+static int gk20a_tsg_unbind_channel_fd(struct tsg_gk20a *tsg, int ch_fd)
+{
+        struct channel_gk20a *ch;
+        int err = 0;
+
+        ch = gk20a_get_channel_from_file(ch_fd);
+        if (!ch)
+                return -EINVAL;
+
+        if (ch->tsgid != tsg->tsgid) {
+                err = -EINVAL;
+                goto out;
+        }
+
+        err = gk20a_tsg_unbind_channel(ch);
+
+        /*
+         * Mark the channel timedout since channel unbound from TSG
+         * has no context of its own so it can't serve any job
+         */
+        gk20a_channel_set_timedout(ch);
+
+out:
+        gk20a_channel_put(ch);
+        return err;
+}
+
+static int gk20a_tsg_get_event_data_from_id(struct tsg_gk20a *tsg,
+                                unsigned int event_id,
+                                struct gk20a_event_id_data **event_id_data)
+{
+        struct gk20a_event_id_data *local_event_id_data;
+        bool event_found = false;
+
+        nvgpu_mutex_acquire(&tsg->event_id_list_lock);
+        nvgpu_list_for_each_entry(local_event_id_data, &tsg->event_id_list,
+                                        gk20a_event_id_data, event_id_node) {
+                if (local_event_id_data->event_id == event_id) {
+                        event_found = true;
+                        break;
+                }
+        }
+        nvgpu_mutex_release(&tsg->event_id_list_lock);
+
+        if (event_found) {
+                *event_id_data = local_event_id_data;
+                return 0;
+        } else {
+                return -1;
+        }
+}
+
+/*
+ * Convert common event_id of the form NVGPU_EVENT_ID_* to Linux specific
+ * event_id of the form NVGPU_IOCTL_CHANNEL_EVENT_ID_* which is used in IOCTLs
+ */
+static u32 nvgpu_event_id_to_ioctl_channel_event_id(u32 event_id)
+{
+        switch (event_id) {
+        case NVGPU_EVENT_ID_BPT_INT:
+                return NVGPU_IOCTL_CHANNEL_EVENT_ID_BPT_INT;
+        case NVGPU_EVENT_ID_BPT_PAUSE:
+                return NVGPU_IOCTL_CHANNEL_EVENT_ID_BPT_PAUSE;
+        case NVGPU_EVENT_ID_BLOCKING_SYNC:
+                return NVGPU_IOCTL_CHANNEL_EVENT_ID_BLOCKING_SYNC;
+        case NVGPU_EVENT_ID_CILP_PREEMPTION_STARTED:
+                return NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_STARTED;
+        case NVGPU_EVENT_ID_CILP_PREEMPTION_COMPLETE:
+                return NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_COMPLETE;
+        case NVGPU_EVENT_ID_GR_SEMAPHORE_WRITE_AWAKEN:
+                return NVGPU_IOCTL_CHANNEL_EVENT_ID_GR_SEMAPHORE_WRITE_AWAKEN;
+        }
+
+        return NVGPU_IOCTL_CHANNEL_EVENT_ID_MAX;
+}
+
+void gk20a_tsg_event_id_post_event(struct tsg_gk20a *tsg,
+                                       int __event_id)
+{
+        struct gk20a_event_id_data *event_id_data;
+        u32 event_id;
+        int err = 0;
+        struct gk20a *g = tsg->g;
+
+        event_id = nvgpu_event_id_to_ioctl_channel_event_id(__event_id);
+        if (event_id >= NVGPU_IOCTL_CHANNEL_EVENT_ID_MAX)
+                return;
+
+        err = gk20a_tsg_get_event_data_from_id(tsg, event_id,
+                                                &event_id_data);
+        if (err)
+                return;
+
+        nvgpu_mutex_acquire(&event_id_data->lock);