diff options
author | Joshua Bakita <bakitajoshua@gmail.com> | 2023-06-28 18:24:25 -0400 |
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committer | Joshua Bakita <bakitajoshua@gmail.com> | 2023-06-28 18:24:25 -0400 |
commit | 01e6fac4d61fdd7fff5433942ec93fc2ea1e4df1 (patch) | |
tree | 4ef34501728a087be24f4ba0af90f91486bf780b /include/os/linux/fuse.c | |
parent | 306a03d18b305e4e573be3b2931978fa10679eb9 (diff) |
Include nvgpu headers
These are needed to build on NVIDIA's Jetson boards for the time
being. Only a couple structs are required, so it should be fairly
easy to remove this dependency at some point in the future.
Diffstat (limited to 'include/os/linux/fuse.c')
-rw-r--r-- | include/os/linux/fuse.c | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/include/os/linux/fuse.c b/include/os/linux/fuse.c new file mode 100644 index 0000000..27851f9 --- /dev/null +++ b/include/os/linux/fuse.c | |||
@@ -0,0 +1,55 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #include <soc/tegra/fuse.h> | ||
15 | |||
16 | #include <nvgpu/fuse.h> | ||
17 | |||
18 | int nvgpu_tegra_get_gpu_speedo_id(struct gk20a *g) | ||
19 | { | ||
20 | return tegra_sku_info.gpu_speedo_id; | ||
21 | } | ||
22 | |||
23 | /* | ||
24 | * Use tegra_fuse_control_read/write() APIs for fuse offsets upto 0x100 | ||
25 | * Use tegra_fuse_readl/writel() APIs for fuse offsets above 0x100 | ||
26 | */ | ||
27 | void nvgpu_tegra_fuse_write_bypass(struct gk20a *g, u32 val) | ||
28 | { | ||
29 | tegra_fuse_control_write(val, FUSE_FUSEBYPASS_0); | ||
30 | } | ||
31 | |||
32 | void nvgpu_tegra_fuse_write_access_sw(struct gk20a *g, u32 val) | ||
33 | { | ||
34 | tegra_fuse_control_write(val, FUSE_WRITE_ACCESS_SW_0); | ||
35 | } | ||
36 | |||
37 | void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(struct gk20a *g, u32 val) | ||
38 | { | ||
39 | tegra_fuse_writel(val, FUSE_OPT_GPU_TPC0_DISABLE_0); | ||
40 | } | ||
41 | |||
42 | void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(struct gk20a *g, u32 val) | ||
43 | { | ||
44 | tegra_fuse_writel(val, FUSE_OPT_GPU_TPC1_DISABLE_0); | ||
45 | } | ||
46 | |||
47 | int nvgpu_tegra_fuse_read_gcplex_config_fuse(struct gk20a *g, u32 *val) | ||
48 | { | ||
49 | return tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, val); | ||
50 | } | ||
51 | |||
52 | int nvgpu_tegra_fuse_read_reserved_calib(struct gk20a *g, u32 *val) | ||
53 | { | ||
54 | return tegra_fuse_readl(FUSE_RESERVED_CALIB0_0, val); | ||
55 | } | ||