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authorJoshua Bakita <bakitajoshua@gmail.com>2024-09-25 16:09:09 -0400
committerJoshua Bakita <bakitajoshua@gmail.com>2024-09-25 16:09:09 -0400
commitf347fde22f1297e4f022600d201780d5ead78114 (patch)
tree76be305d6187003a1e0486ff6e91efb1062ae118 /include/nvgpu/posix/io.h
parent8340d234d78a7d0f46c11a584de538148b78b7cb (diff)
Delete no-longer-needed nvgpu headersHEADmasterjbakita-wip
The dependency on these was removed in commit 8340d234.
Diffstat (limited to 'include/nvgpu/posix/io.h')
-rw-r--r--include/nvgpu/posix/io.h114
1 files changed, 0 insertions, 114 deletions
diff --git a/include/nvgpu/posix/io.h b/include/nvgpu/posix/io.h
deleted file mode 100644
index 98be4d0..0000000
--- a/include/nvgpu/posix/io.h
+++ /dev/null
@@ -1,114 +0,0 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef NVGPU_POSIX_IO_H
24#define NVGPU_POSIX_IO_H
25
26#include <nvgpu/types.h>
27#include <nvgpu/list.h>
28
29struct gk20a;
30
31/**
32 * Here lies the interface for a unit test module to interact with the nvgpu IO
33 * accessors. This interface provides the ability for a module to react to nvgpu
34 * calling nvgpu IO accessors so that nvgpu can handle various HW sequences even
35 * when run in unit testing mode.
36 *
37 * The primary interface is simply callbacks to the unit test module which the
38 * module can handle how ever it wishes.
39 */
40
41struct nvgpu_reg_access {
42 /*
43 * Address of the register write relative to the base of the register
44 * space. I.e you can compare this against values in the HW headers
45 * directly to check what register is being read/written to/from.
46 */
47 u32 addr;
48
49 /*
50 * Writes: this is the value being written.
51 * Reads: populate with the value to return.
52 */
53 u32 value;
54};
55
56struct nvgpu_posix_io_callbacks {
57 void (*writel)(struct gk20a *g, struct nvgpu_reg_access *access);
58 void (*writel_check)(struct gk20a *g, struct nvgpu_reg_access *access);
59 void (*__readl)(struct gk20a *g, struct nvgpu_reg_access *access);
60 void (*readl)(struct gk20a *g, struct nvgpu_reg_access *access);
61 void (*bar1_writel)(struct gk20a *g, struct nvgpu_reg_access *access);
62 void (*bar1_readl)(struct gk20a *g, struct nvgpu_reg_access *access);
63 void (*usermode_writel)(struct gk20a *g,
64 struct nvgpu_reg_access *access);
65};
66
67struct nvgpu_posix_io_callbacks *nvgpu_posix_register_io(
68 struct gk20a *g,
69 struct nvgpu_posix_io_callbacks *io_callbacks);
70
71struct nvgpu_posix_io_reg_space {
72 u32 base;
73 u32 size;
74 u32 *data;
75 struct nvgpu_list_node link;
76};
77
78static inline struct nvgpu_posix_io_reg_space *
79nvgpu_posix_io_reg_space_from_link(struct nvgpu_list_node *node)
80{
81 return (struct nvgpu_posix_io_reg_space *)
82 ((uintptr_t)node - offsetof(struct nvgpu_posix_io_reg_space, link));
83};
84
85void nvgpu_posix_io_init_reg_space(struct gk20a *g);
86int nvgpu_posix_io_get_error_code(struct gk20a *g);
87void nvgpu_posix_io_reset_error_code(struct gk20a *g);
88int nvgpu_posix_io_add_reg_space(struct gk20a *g, u32 base, u32 size);
89struct nvgpu_posix_io_reg_space *nvgpu_posix_io_get_reg_space(struct gk20a *g,
90 u32 addr);
91void nvgpu_posix_io_delete_reg_space(struct gk20a *g, u32 base);
92void nvgpu_posix_io_writel_reg_space(struct gk20a *g, u32 addr, u32 data);
93u32 nvgpu_posix_io_readl_reg_space(struct gk20a *g, u32 addr);
94
95struct nvgpu_posix_io_reg_access {
96 struct nvgpu_reg_access access;
97 struct nvgpu_list_node link;
98};
99
100static inline struct nvgpu_posix_io_reg_access *
101nvgpu_posix_io_reg_access_from_link(struct nvgpu_list_node *node)
102{
103 return (struct nvgpu_posix_io_reg_access *)
104 ((uintptr_t)node - offsetof(struct nvgpu_posix_io_reg_access, link));
105};
106
107void nvgpu_posix_io_start_recorder(struct gk20a *g);
108void nvgpu_posix_io_reset_recorder(struct gk20a *g);
109void nvgpu_posix_io_record_access(struct gk20a *g,
110 struct nvgpu_reg_access *access);
111bool nvgpu_posix_io_check_sequence(struct gk20a *g,
112 struct nvgpu_reg_access *sequence, u32 size, bool strict);
113
114#endif