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author | Joshua Bakita <bakitajoshua@gmail.com> | 2024-09-25 16:09:09 -0400 |
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committer | Joshua Bakita <bakitajoshua@gmail.com> | 2024-09-25 16:09:09 -0400 |
commit | f347fde22f1297e4f022600d201780d5ead78114 (patch) | |
tree | 76be305d6187003a1e0486ff6e91efb1062ae118 /include/nvgpu/posix/atomic.h | |
parent | 8340d234d78a7d0f46c11a584de538148b78b7cb (diff) |
Delete no-longer-needed nvgpu headersHEADmasterjbakita-wip
The dependency on these was removed in commit 8340d234.
Diffstat (limited to 'include/nvgpu/posix/atomic.h')
-rw-r--r-- | include/nvgpu/posix/atomic.h | 191 |
1 files changed, 0 insertions, 191 deletions
diff --git a/include/nvgpu/posix/atomic.h b/include/nvgpu/posix/atomic.h deleted file mode 100644 index c9d9212..0000000 --- a/include/nvgpu/posix/atomic.h +++ /dev/null | |||
@@ -1,191 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef __NVGPU_POSIX_ATOMIC_H__ | ||
24 | #define __NVGPU_POSIX_ATOMIC_H__ | ||
25 | |||
26 | #include <nvgpu/types.h> | ||
27 | |||
28 | /* | ||
29 | * Note: this code uses the GCC builtins to implement atomics. | ||
30 | */ | ||
31 | |||
32 | #define __atomic_cmpxchg(p, v, c) __sync_val_compare_and_swap(p, v, c) | ||
33 | #define __atomic_and(p, v) __sync_fetch_and_and(p, v) | ||
34 | #define __atomic_or(p, v) __sync_fetch_and_or(p, v) | ||
35 | |||
36 | #define cmpxchg __atomic_cmpxchg | ||
37 | |||
38 | /* | ||
39 | * Place holders until real atomics can be implemented... Yay for GCC builtins! | ||
40 | * We can use those eventually to define all the Linux atomic ops. | ||
41 | * | ||
42 | * TODO: make these _actually_ atomic! | ||
43 | */ | ||
44 | typedef struct __nvgpu_posix_atomic { | ||
45 | int v; | ||
46 | } nvgpu_atomic_t; | ||
47 | |||
48 | typedef struct __nvgpu_posix_atomic64 { | ||
49 | long v; | ||
50 | } nvgpu_atomic64_t; | ||
51 | |||
52 | #define __nvgpu_atomic_init(i) { i } | ||
53 | #define __nvgpu_atomic64_init(i) { i } | ||
54 | |||
55 | static inline void __nvgpu_atomic_set(nvgpu_atomic_t *v, int i) | ||
56 | { | ||
57 | v->v = i; | ||
58 | } | ||
59 | |||
60 | static inline int __nvgpu_atomic_read(nvgpu_atomic_t *v) | ||
61 | { | ||
62 | return v->v; | ||
63 | } | ||
64 | |||
65 | static inline void __nvgpu_atomic_inc(nvgpu_atomic_t *v) | ||
66 | { | ||
67 | v->v++; | ||
68 | } | ||
69 | |||
70 | static inline int __nvgpu_atomic_inc_return(nvgpu_atomic_t *v) | ||
71 | { | ||
72 | v->v++; | ||
73 | return v->v; | ||
74 | } | ||
75 | |||
76 | static inline void __nvgpu_atomic_dec(nvgpu_atomic_t *v) | ||
77 | { | ||
78 | v->v--; | ||
79 | } | ||
80 | |||
81 | static inline int __nvgpu_atomic_dec_return(nvgpu_atomic_t *v) | ||
82 | { | ||
83 | v->v--; | ||
84 | return v->v; | ||
85 | } | ||
86 | |||
87 | static inline int __nvgpu_atomic_cmpxchg(nvgpu_atomic_t *v, int old, int new) | ||
88 | { | ||
89 | if (v->v == old) | ||
90 | v->v = new; | ||
91 | |||
92 | return v->v; | ||
93 | } | ||
94 | |||
95 | static inline int __nvgpu_atomic_xchg(nvgpu_atomic_t *v, int new) | ||
96 | { | ||
97 | v->v = new; | ||
98 | return new; | ||
99 | } | ||
100 | |||
101 | static inline bool __nvgpu_atomic_inc_and_test(nvgpu_atomic_t *v) | ||
102 | { | ||
103 | v->v++; | ||
104 | return v->v ? true : false; | ||
105 | } | ||
106 | |||
107 | static inline bool __nvgpu_atomic_dec_and_test(nvgpu_atomic_t *v) | ||
108 | { | ||
109 | v->v--; | ||
110 | return v->v ? true : false; | ||
111 | } | ||
112 | |||
113 | static inline bool __nvgpu_atomic_sub_and_test(int i, nvgpu_atomic_t *v) | ||
114 | { | ||
115 | v->v -= i; | ||
116 | return v->v ? true : false; | ||
117 | } | ||
118 | |||
119 | static inline int __nvgpu_atomic_add_return(int i, nvgpu_atomic_t *v) | ||
120 | { | ||
121 | v->v += i; | ||
122 | return v->v; | ||
123 | } | ||
124 | |||
125 | static inline int __nvgpu_atomic_add_unless(nvgpu_atomic_t *v, int a, int u) | ||
126 | { | ||
127 | if (v->v != u) | ||
128 | v->v += a; | ||
129 | |||
130 | return v->v; | ||
131 | } | ||
132 | |||
133 | static inline void __nvgpu_atomic64_set(nvgpu_atomic64_t *v, long i) | ||
134 | { | ||
135 | v->v = i; | ||
136 | } | ||
137 | |||
138 | static inline long __nvgpu_atomic64_read(nvgpu_atomic64_t *v) | ||
139 | { | ||
140 | return v->v; | ||
141 | } | ||
142 | |||
143 | static inline void __nvgpu_atomic64_add(long x, nvgpu_atomic64_t *v) | ||
144 | { | ||
145 | v->v += x; | ||
146 | } | ||
147 | |||
148 | static inline void __nvgpu_atomic64_inc(nvgpu_atomic64_t *v) | ||
149 | { | ||
150 | v->v++; | ||
151 | } | ||
152 | |||
153 | static inline long __nvgpu_atomic64_inc_return(nvgpu_atomic64_t *v) | ||
154 | { | ||
155 | v->v++; | ||
156 | return v->v; | ||
157 | } | ||
158 | |||
159 | static inline void __nvgpu_atomic64_dec(nvgpu_atomic64_t *v) | ||
160 | { | ||
161 | v->v--; | ||
162 | } | ||
163 | |||
164 | static inline long __nvgpu_atomic64_dec_return(nvgpu_atomic64_t *v) | ||
165 | { | ||
166 | v->v--; | ||
167 | return v->v; | ||
168 | } | ||
169 | |||
170 | static inline long __nvgpu_atomic64_cmpxchg(nvgpu_atomic64_t *v, | ||
171 | long old, long new) | ||
172 | { | ||
173 | |||
174 | if (v->v == old) | ||
175 | v->v = new; | ||
176 | |||
177 | return v->v; | ||
178 | } | ||
179 | |||
180 | static inline void __nvgpu_atomic64_sub(long x, nvgpu_atomic64_t *v) | ||
181 | { | ||
182 | v->v -= x; | ||
183 | } | ||
184 | |||
185 | static inline long __nvgpu_atomic64_sub_return(long x, nvgpu_atomic64_t *v) | ||
186 | { | ||
187 | v->v -= x; | ||
188 | return v->v; | ||
189 | } | ||
190 | |||
191 | #endif | ||