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authorJoshua Bakita <bakitajoshua@gmail.com>2024-09-25 16:09:09 -0400
committerJoshua Bakita <bakitajoshua@gmail.com>2024-09-25 16:09:09 -0400
commitf347fde22f1297e4f022600d201780d5ead78114 (patch)
tree76be305d6187003a1e0486ff6e91efb1062ae118 /include/nvgpu/pmuif/gpmuifclk.h
parent8340d234d78a7d0f46c11a584de538148b78b7cb (diff)
Delete no-longer-needed nvgpu headers
The dependency on these was removed in commit 8340d234.
Diffstat (limited to 'include/nvgpu/pmuif/gpmuifclk.h')
-rw-r--r--include/nvgpu/pmuif/gpmuifclk.h573
1 files changed, 0 insertions, 573 deletions
diff --git a/include/nvgpu/pmuif/gpmuifclk.h b/include/nvgpu/pmuif/gpmuifclk.h
deleted file mode 100644
index 70a913b..0000000
--- a/include/nvgpu/pmuif/gpmuifclk.h
+++ /dev/null
@@ -1,573 +0,0 @@
1/*
2* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3*
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21*/
22
23#ifndef NVGPU_PMUIF_GPMUIFCLK_H
24#define NVGPU_PMUIF_GPMUIFCLK_H
25
26#include "ctrl/ctrlboardobj.h"
27#include "ctrl/ctrlvolt.h"
28#include "ctrl/ctrlperf.h"
29#include "ctrl/ctrlclk.h"
30#include "gpmuifboardobj.h"
31#include "gpmuifvolt.h"
32#include <nvgpu/flcnif_cmn.h>
33
34
35/*
36 * Try to get gpc2clk, mclk, sys2clk, xbar2clk work for Pascal
37 *
38 * mclk is same for both
39 * gpc2clk is 17 for Pascal and 13 for Volta, making it 17
40 * as volta uses gpcclk
41 * sys2clk is 20 in Pascal and 15 in Volta.
42 * Changing for Pascal would break nvdclk of Volta
43 * xbar2clk is 19 in Pascal and 14 in Volta
44 * Changing for Pascal would break pwrclk of Volta
45 */
46enum nv_pmu_clk_clkwhich {
47 clkwhich_gpcclk = 1,
48 clkwhich_xbarclk = 2,
49 clkwhich_sysclk = 3,
50 clkwhich_hubclk = 4,
51 clkwhich_mclk = 5,
52 clkwhich_hostclk = 6,
53 clkwhich_dispclk = 7,
54 clkwhich_xclk = 12,
55 clkwhich_gpc2clk = 17,
56 clkwhich_xbar2clk = 14,
57 clkwhich_sys2clk = 15,
58 clkwhich_hub2clk = 16,
59 clkwhich_pwrclk = 19,
60 clkwhich_nvdclk = 20,
61 clkwhich_pciegenclk = 26,
62};
63
64/*
65 * Enumeration of BOARDOBJGRP class IDs within OBJCLK. Used as "classId"
66 * argument for communications between Kernel and PMU via the various generic
67 * BOARDOBJGRP interfaces.
68 */
69#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_DOMAIN 0x00
70#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_PROG 0x01
71#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_VIN_DEVICE 0x02
72#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_FLL_DEVICE 0x03
73#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_VF_POINT 0x04
74#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_FREQ_CONTROLLER 0x05
75
76/*!
77* CLK_DOMAIN BOARDOBJGRP Header structure. Describes global state about the
78* CLK_DOMAIN feature.
79*/
80struct nv_pmu_clk_clk_domain_boardobjgrp_set_header {
81 struct nv_pmu_boardobjgrp_e32 super;
82 u32 vbios_domains;
83 struct ctrl_boardobjgrp_mask_e32 prog_domains_mask;
84 struct ctrl_boardobjgrp_mask_e32 master_domains_mask;
85 u16 cntr_sampling_periodms;
86 u8 version;
87 bool b_override_o_v_o_c;
88 bool b_debug_mode;
89 bool b_enforce_vf_monotonicity;
90 bool b_enforce_vf_smoothening;
91 u8 volt_rails_max;
92 struct ctrl_clk_clk_delta deltas;
93};
94
95struct nv_pmu_clk_clk_domain_boardobj_set {
96 struct nv_pmu_boardobj super;
97 enum nv_pmu_clk_clkwhich domain;
98 u32 api_domain;
99 u8 perf_domain_grp_idx;
100};
101
102struct nv_pmu_clk_clk_domain_3x_boardobj_set {
103 struct nv_pmu_clk_clk_domain_boardobj_set super;
104 bool b_noise_aware_capable;
105};
106
107struct nv_pmu_clk_clk_domain_3x_fixed_boardobj_set {
108 struct nv_pmu_clk_clk_domain_3x_boardobj_set super;
109 u16 freq_mhz;
110};
111
112struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set {
113 struct nv_pmu_clk_clk_domain_3x_boardobj_set super;
114 u8 clk_prog_idx_first;
115 u8 clk_prog_idx_last;
116 bool b_force_noise_unaware_ordering;
117 struct ctrl_clk_freq_delta factory_delta;
118 short freq_delta_min_mhz;
119 short freq_delta_max_mhz;
120 struct ctrl_clk_clk_delta deltas;
121};
122
123struct nv_pmu_clk_clk_domain_30_prog_boardobj_set {
124 struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super;
125 u8 noise_unaware_ordering_index;
126 u8 noise_aware_ordering_index;
127};
128
129struct nv_pmu_clk_clk_domain_3x_master_boardobj_set {
130 u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */
131 u32 slave_idxs_mask;
132};
133
134struct nv_pmu_clk_clk_domain_30_master_boardobj_set {
135 struct nv_pmu_clk_clk_domain_30_prog_boardobj_set super;
136 struct nv_pmu_clk_clk_domain_3x_master_boardobj_set master;
137};
138
139struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set {
140 u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */
141 u8 master_idx;
142};
143
144struct nv_pmu_clk_clk_domain_30_slave_boardobj_set {
145 struct nv_pmu_clk_clk_domain_30_prog_boardobj_set super;
146 struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set slave;
147};
148
149struct nv_pmu_clk_clk_domain_35_prog_boardobj_set {
150 struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super;
151 u8 pre_volt_ordering_index;
152 u8 post_volt_ordering_index;
153 u8 clk_pos;
154 u8 clk_vf_curve_count;
155};
156
157struct nv_pmu_clk_clk_domain_35_master_boardobj_set {
158 struct nv_pmu_clk_clk_domain_35_prog_boardobj_set super;
159 struct nv_pmu_clk_clk_domain_3x_master_boardobj_set master;
160 u32 master_slave_domains_grp_mask;
161};
162
163
164struct nv_pmu_clk_clk_domain_35_slave_boardobj_set {
165 struct nv_pmu_clk_clk_domain_35_prog_boardobj_set super;
166 struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set slave;
167};
168
169union nv_pmu_clk_clk_domain_boardobj_set_union {
170 struct nv_pmu_boardobj board_obj;
171 struct nv_pmu_clk_clk_domain_boardobj_set super;
172 struct nv_pmu_clk_clk_domain_3x_boardobj_set v3x;
173 struct nv_pmu_clk_clk_domain_3x_fixed_boardobj_set v3x_fixed;
174 struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set v3x_prog;
175 struct nv_pmu_clk_clk_domain_30_prog_boardobj_set v30_prog;
176 struct nv_pmu_clk_clk_domain_30_master_boardobj_set v30_master;
177 struct nv_pmu_clk_clk_domain_30_slave_boardobj_set v30_slave;
178 struct nv_pmu_clk_clk_domain_35_prog_boardobj_set v35_prog;
179 struct nv_pmu_clk_clk_domain_35_master_boardobj_set v35_master;
180 struct nv_pmu_clk_clk_domain_35_slave_boardobj_set v35_slave;
181};
182
183NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_domain);
184
185struct nv_pmu_clk_clk_prog_boardobjgrp_set_header {
186 struct nv_pmu_boardobjgrp_e255 super;
187 u8 slave_entry_count;
188 u8 vf_entry_count;
189};
190
191struct nv_pmu_clk_clk_prog_boardobj_set {
192 struct nv_pmu_boardobj super;
193};
194
195struct nv_pmu_clk_clk_prog_1x_boardobj_set {
196 struct nv_pmu_clk_clk_prog_boardobj_set super;
197 u8 source;
198 u16 freq_max_mhz;
199 union ctrl_clk_clk_prog_1x_source_data source_data;
200};
201
202struct nv_pmu_clk_clk_prog_1x_master_boardobj_set {
203 struct nv_pmu_clk_clk_prog_1x_boardobj_set super;
204 u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */
205 bool b_o_c_o_v_enabled;
206 struct ctrl_clk_clk_prog_1x_master_vf_entry vf_entries[
207 CTRL_CLK_CLK_PROG_1X_MASTER_VF_ENTRY_MAX_ENTRIES];
208 struct ctrl_clk_clk_delta deltas;
209 union ctrl_clk_clk_prog_1x_master_source_data source_data;
210};