diff options
author | Joshua Bakita <bakitajoshua@gmail.com> | 2024-09-25 16:09:09 -0400 |
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committer | Joshua Bakita <bakitajoshua@gmail.com> | 2024-09-25 16:09:09 -0400 |
commit | f347fde22f1297e4f022600d201780d5ead78114 (patch) | |
tree | 76be305d6187003a1e0486ff6e91efb1062ae118 /include/nvgpu/pmuif/gpmuif_perfmon.h | |
parent | 8340d234d78a7d0f46c11a584de538148b78b7cb (diff) |
Delete no-longer-needed nvgpu headersHEADmasterjbakita-wip
The dependency on these was removed in commit 8340d234.
Diffstat (limited to 'include/nvgpu/pmuif/gpmuif_perfmon.h')
-rw-r--r-- | include/nvgpu/pmuif/gpmuif_perfmon.h | 241 |
1 files changed, 0 insertions, 241 deletions
diff --git a/include/nvgpu/pmuif/gpmuif_perfmon.h b/include/nvgpu/pmuif/gpmuif_perfmon.h deleted file mode 100644 index 8324e36..0000000 --- a/include/nvgpu/pmuif/gpmuif_perfmon.h +++ /dev/null | |||
@@ -1,241 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | #ifndef NVGPU_PMUIF_GPMUIF_PERFMON_H | ||
23 | #define NVGPU_PMUIF_GPMUIF_PERFMON_H | ||
24 | |||
25 | /*perfmon task defines*/ | ||
26 | |||
27 | #define PMU_DOMAIN_GROUP_PSTATE 0 | ||
28 | #define PMU_DOMAIN_GROUP_GPC2CLK 1 | ||
29 | #define PMU_DOMAIN_GROUP_NUM 2 | ||
30 | |||
31 | #define PMU_PERFMON_FLAG_ENABLE_INCREASE (0x00000001) | ||
32 | #define PMU_PERFMON_FLAG_ENABLE_DECREASE (0x00000002) | ||
33 | #define PMU_PERFMON_FLAG_CLEAR_PREV (0x00000004) | ||
34 | |||
35 | #define NV_PMU_PERFMON_MAX_COUNTERS 10U | ||
36 | |||
37 | enum pmu_perfmon_cmd_start_fields { | ||
38 | COUNTER_ALLOC | ||
39 | }; | ||
40 | |||
41 | enum { | ||
42 | PMU_PERFMON_CMD_ID_START = 0, | ||
43 | PMU_PERFMON_CMD_ID_STOP = 1, | ||
44 | PMU_PERFMON_CMD_ID_INIT = 2 | ||
45 | }; | ||
46 | |||
47 | struct pmu_perfmon_counter_v2 { | ||
48 | u8 index; | ||
49 | u8 flags; | ||
50 | u8 group_id; | ||
51 | u8 valid; | ||
52 | u16 upper_threshold; /* units of 0.01% */ | ||
53 | u16 lower_threshold; /* units of 0.01% */ | ||
54 | u32 scale; | ||
55 | }; | ||
56 | |||
57 | struct pmu_perfmon_counter_v3 { | ||
58 | u8 index; | ||
59 | u8 group_id; | ||
60 | u16 flags; | ||
61 | u16 upper_threshold; /* units of 0.01% */ | ||
62 | u16 lower_threshold; /* units of 0.01% */ | ||
63 | u32 scale; | ||
64 | }; | ||
65 | |||
66 | struct pmu_perfmon_cmd_start_v3 { | ||
67 | u8 cmd_type; | ||
68 | u8 group_id; | ||
69 | u8 state_id; | ||
70 | u8 flags; | ||
71 | struct pmu_allocation_v3 counter_alloc; | ||
72 | }; | ||
73 | |||
74 | struct pmu_perfmon_cmd_start_v2 { | ||
75 | u8 cmd_type; | ||
76 | u8 group_id; | ||
77 | u8 state_id; | ||
78 | u8 flags; | ||
79 | struct pmu_allocation_v2 counter_alloc; | ||
80 | }; | ||
81 | |||
82 | struct pmu_perfmon_cmd_start_v1 { | ||
83 | u8 cmd_type; | ||
84 | u8 group_id; | ||
85 | u8 state_id; | ||
86 | u8 flags; | ||
87 | struct pmu_allocation_v1 counter_alloc; | ||
88 | }; | ||
89 | |||
90 | struct pmu_perfmon_cmd_stop { | ||
91 | u8 cmd_type; | ||
92 | }; | ||
93 | |||
94 | struct pmu_perfmon_cmd_init_v3 { | ||
95 | u8 cmd_type; | ||
96 | u8 to_decrease_count; | ||
97 | u8 base_counter_id; | ||
98 | u32 sample_period_us; | ||
99 | struct pmu_allocation_v3 counter_alloc; | ||
100 | u8 num_counters; | ||
101 | u8 samples_in_moving_avg; | ||
102 | u16 sample_buffer; | ||
103 | }; | ||
104 | |||
105 | struct pmu_perfmon_cmd_init_v2 { | ||
106 | u8 cmd_type; | ||
107 | u8 to_decrease_count; | ||
108 | u8 base_counter_id; | ||
109 | u32 sample_period_us; | ||
110 | struct pmu_allocation_v2 counter_alloc; | ||
111 | u8 num_counters; | ||
112 | u8 samples_in_moving_avg; | ||
113 | u16 sample_buffer; | ||
114 | }; | ||
115 | |||
116 | struct pmu_perfmon_cmd_init_v1 { | ||
117 | u8 cmd_type; | ||
118 | u8 to_decrease_count; | ||
119 | u8 base_counter_id; | ||
120 | u32 sample_period_us; | ||
121 | struct pmu_allocation_v1 counter_alloc; | ||
122 | u8 num_counters; | ||
123 | u8 samples_in_moving_avg; | ||
124 | u16 sample_buffer; | ||
125 | }; | ||
126 | |||
127 | struct pmu_perfmon_cmd { | ||
128 | union { | ||
129 | u8 cmd_type; | ||
130 | struct pmu_perfmon_cmd_start_v1 start_v1; | ||
131 | struct pmu_perfmon_cmd_start_v2 start_v2; | ||
132 | struct pmu_perfmon_cmd_start_v3 start_v3; | ||
133 | struct pmu_perfmon_cmd_stop stop; | ||
134 | struct pmu_perfmon_cmd_init_v1 init_v1; | ||
135 | struct pmu_perfmon_cmd_init_v2 init_v2; | ||
136 | struct pmu_perfmon_cmd_init_v3 init_v3; | ||
137 | }; | ||
138 | }; | ||
139 | |||
140 | struct pmu_zbc_cmd { | ||
141 | u8 cmd_type; | ||
142 | u8 pad; | ||
143 | u16 entry_mask; | ||
144 | }; | ||
145 | |||
146 | /* PERFMON MSG */ | ||
147 | enum { | ||
148 | PMU_PERFMON_MSG_ID_INCREASE_EVENT = 0, | ||
149 | PMU_PERFMON_MSG_ID_DECREASE_EVENT = 1, | ||
150 | PMU_PERFMON_MSG_ID_INIT_EVENT = 2, | ||
151 | PMU_PERFMON_MSG_ID_ACK = 3 | ||
152 | }; | ||
153 | |||
154 | struct pmu_perfmon_msg_generic { | ||
155 | u8 msg_type; | ||
156 | u8 state_id; | ||
157 | u8 group_id; | ||
158 | u8 data; | ||
159 | }; | ||
160 | |||
161 | struct pmu_perfmon_msg { | ||
162 | union { | ||
163 | u8 msg_type; | ||
164 | struct pmu_perfmon_msg_generic gen; | ||
165 | }; | ||
166 | }; | ||
167 | |||
168 | /* PFERMON RPC interface*/ | ||
169 | /* | ||
170 | * RPC calls serviced by PERFMON unit. | ||
171 | */ | ||
172 | #define NV_PMU_RPC_ID_PERFMON_T18X_INIT 0x00 | ||
173 | #define NV_PMU_RPC_ID_PERFMON_T18X_DEINIT 0x01 | ||
174 | #define NV_PMU_RPC_ID_PERFMON_T18X_START 0x02 | ||
175 | #define NV_PMU_RPC_ID_PERFMON_T18X_STOP 0x03 | ||
176 | #define NV_PMU_RPC_ID_PERFMON_T18X_QUERY 0x04 | ||
177 | #define NV_PMU_RPC_ID_PERFMON_T18X__COUNT 0x05 | ||
178 | |||
179 | /* | ||
180 | * structure that holds data used to | ||
181 | * execute Perfmon INIT RPC. | ||
182 | * hdr - RPC header | ||
183 | * sample_periodus - Desired period in between samples. | ||
184 | * to_decrease_count - Consecutive samples before decrease event. | ||
185 | * base_counter_id - Index of the base counter. | ||
186 | * samples_in_moving_avg - Number of values in moving average. | ||
187 | * num_counters - Num of counters PMU should use. | ||
188 | * counter - Counters. | ||
189 | */ | ||
190 | struct nv_pmu_rpc_struct_perfmon_init { | ||
191 | struct nv_pmu_rpc_header hdr; | ||
192 | u32 sample_periodus; | ||
193 | u8 to_decrease_count; | ||
194 | u8 base_counter_id; | ||
195 | u8 samples_in_moving_avg; | ||
196 | u8 num_counters; | ||
197 | struct pmu_perfmon_counter_v3 counter[NV_PMU_PERFMON_MAX_COUNTERS]; | ||
198 | u32 scratch[1]; | ||
199 | }; | ||
200 | |||
201 | /* | ||
202 | * structure that holds data used to | ||
203 | * execute Perfmon START RPC. | ||
204 | * hdr - RPC header | ||
205 | * group_id - NV group ID | ||
206 | * state_id - NV state ID | ||
207 | * flags - PMU_PERFON flags | ||
208 | * counters - Counters. | ||
209 | */ | ||
210 | struct nv_pmu_rpc_struct_perfmon_start { | ||
211 | struct nv_pmu_rpc_header hdr; | ||
212 | u8 group_id; | ||
213 | u8 state_id; | ||
214 | u8 flags; | ||
215 | struct pmu_perfmon_counter_v3 counter[NV_PMU_PERFMON_MAX_COUNTERS]; | ||
216 | u32 scratch[1]; | ||
217 | }; | ||
218 | |||
219 | /* | ||
220 | * structure that holds data used to | ||
221 | * execute Perfmon STOP RPC. | ||
222 | * hdr - RPC header | ||
223 | */ | ||
224 | struct nv_pmu_rpc_struct_perfmon_stop { | ||
225 | struct nv_pmu_rpc_header hdr; | ||
226 | u32 scratch[1]; | ||
227 | }; | ||
228 | |||
229 | /* | ||
230 | * structure that holds data used to | ||
231 | * execute QUERY RPC. | ||
232 | * hdr - RPC header | ||
233 | * sample_buffer - Output buffer from pmu containing utilization samples. | ||
234 | */ | ||
235 | struct nv_pmu_rpc_struct_perfmon_query { | ||
236 | struct nv_pmu_rpc_header hdr; | ||
237 | u16 sample_buffer[NV_PMU_PERFMON_MAX_COUNTERS]; | ||
238 | u32 scratch[1]; | ||
239 | }; | ||
240 | |||
241 | #endif /* NVGPU_PMUIF_GPMUIF_PERFMON_H */ | ||